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Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm


Dynamic random access memory (DRAM) cells are commonly used in electronic devices and are formed from a single transistor and capacitor. Alternative approaches, which are based on the floating body effect, have been proposed that could reduce manufacturing complexity and minimize the cell footprint by removing the external capacitor. Such capacitor-less DRAM has been demonstrated in silicon, but the use of other materials, including III–V compound semiconductors, remains relatively unexplored, despite the fact that they could lead to enhanced performance. Here we report capacitor-less one-transistor DRAM cells based on indium gallium arsenide (InGaAs). With our InGaAs on insulator transistors, we demonstrate different current levels for each logic state, and thus successful memory behaviour, down to a gate length of 14 nm.

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Fig. 1: Operation details of an MSDRAM memory cell.
Fig. 2: InGaAs-OI transistor structure and non-calibrated TCAD results.
Fig. 3: Front- and back-channel static d.c. characteristics.
Fig. 4: Experimental III–V InGaAs-OI capacitor-less DRAM cell demonstration.
Fig. 5: Reduced ‘1’-state writing power demonstration and current levels.
Fig. 6: Experimental retention time on ultra-scaled InGaAs-OI cell.

Data availability

The data supporting the plots within this paper and other findings in this study are available from the corresponding author upon reasonable request.


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H2020 REMINDER (grant no. 687931) and H2020 INSIGHT (grant no. 688784) European projects are acknowledged for financial support.

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C.N. carried out the experiments, wrote the initial manuscript and performed the TCAD simulations. S.K. provided fabrication details and actively participated in the experimental characterization. C.M. helped with the experimental set-up and later data analysis. S.N. took care of the graphics design and processed the experimental and simulation data. C.C., C.Z. and L.C. fabricated the MSDRAM samples. F.G. coordinated and supervised the whole work. All authors discussed the results and revised and commented on the manuscript.

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Correspondence to Carlos Navarro.

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Navarro, C., Karg, S., Marquez, C. et al. Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm. Nat Electron 2, 412–419 (2019).

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