The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated.
Subscribe to Journal
Get full journal access for 1 year
only $8.67 per issue
All prices are NET prices.
VAT will be added later in the checkout.
Rent or Buy article
Get time limited or full article access on ReadCube.
All prices are NET prices.
The data that support the plots within this paper and other findings of this study are available from the corresponding author on reasonable request.
Moore, G. E. Cramming more components onto integrated circuits. Electronics 38, 114–117 (1965).
Peercy, P. S. The drive to miniaturization. Nature 406, 1023–1026 (2000).
Smith, K. C. The prospects for multivalued logic: a technology and applications view. IEEE Trans. Comput. C-30, 619–634 (1981).
Hurst, S. L. Multiple-valued logic—its status and its future. IEEE Trans. Comput. C-33, 1160–1179 (1984).
Esser, S. K. Convolutional networks for fast, energy-efficient neuromorphic computing. Proc. Natl Acad. Sci. USA 113, 11441–11446 (2016).
Lennie, P. The cost of cortical computation. Curr. Biol. 13, 493–497 (2003).
Merolla, P. A. et al. A million spiking-neuron integrated circuit with a scalable communication network and interface. Science 345, 668–672 (2014).
Davies, M. et al. Loihi: a neuromorphic manycore processor with on-chip learning. IEEE Micro 38, 82–99 (2018).
Mouftah, H. T. & Jordan, I. B. Design of ternary COS/MOS memory and sequential circuits. IEEE Trans. Comput. C-26, 281–288 (1977).
Heung, A. & Mouftah, H. T. Depletion/enhancement CMOS for a lower power family of three-valued logic circuits. IEEE J. Solid-State Circuits 20, 609–616 (1985).
Raychowdhury, A. & Roy, K. Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4, 168–179 (2005).
Karmakar, S. Ternary logic gates using quantum dot gate FETs (QDGFETs). Silicon 6, 169–178 (2014).
Shim, J. et al. Phosphorene/rhenium disulfide heterojunction-based negative differential resistance device for multi-valued logic. Nat. Commun. 7, 13413 (2016).
Kim, Y. J. et al. Demonstration of complementary ternary graphene field-effect transistors. Sci. Rep. 6, 39353 (2016).
Heo, S. et al. Ternary full adder using multi-threshold voltage graphene barristors. IEEE Electron Device Lett. 39, 1948–1951 (2018).
Kane, E. O. Zener tunneling in semiconductors. J. Phys. Chem. Solids 12, 181–188 (1960).
Taur, Y. & Ning, T. H. in Fundamentals of Modern VLSI Devices 2nd edn 125–126 (Cambridge Univ. Press, 2009).
Kim, K. R. et al. Silicon-based field-induced band-to-band tunneling effect transistor. IEEE Electron Device Lett. 25, 439–441 (2004).
Ionescu, A. M. & Riel, Heike Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011).
Sarkar, D. et al. A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature 526, 91–95 (2015).
Shin, S., Jang, E., Jeong, J. W., Park, B.-G. & Kim, K. R. Compact design of low power standard ternary inverter based on OFF-state current mechanism using nano-CMOS technology. IEEE Trans. Electron Devices 62, 2396–2403 (2015).
Shin, S., Jang, E., Jeong, J. W. & Kim, K. R. In 2017 IEEE Int. Symp. Multi-Valued Logic (ISMVL) 284–289 (IEEE, 2017); https://doi.org/10.1109/ISMVL.2017.48
Taur, Y., Wann, C. H. & Frank, D. J. In 1998 IEEE Int. Electron Devices Meet. 789–792 (IEEE, 1998); https://doi.org/10.1109/IEDM.1998.746474
Borse, D. G. et al. Optimization and realization of sub-100-nm channel length single halo p-MOSFETs. IEEE Trans. Electron Devices 49, 1077–1079 (2002).
Fujita, K. et al. In 2011 IEEE Int. Electron Devices Meet. 749–752 (IEEE, 2011); https://doi.org/10.1109/IEDM.2011.6131657
Zhang, X. et al. Comparison of SOI versus bulk FinFET technologies for 6T-SRAM voltage scaling at the 7-/8-nm node. IEEE Trans. Electron Devices 64, 329–332 (2017).
Yoshitomi, T. et al. In 1993 Symp. VLSI Tech. 99–100 (IEEE, 1993); https://doi.org/10.1109/VLSIT.1993.760264
Toyoshima, Y., Eguchi, T., Hayashida, H. & Hashimoto, K. In 1991 Symp. VLSI Tech. 111–112 (IEEE, 1991); https://doi.org/10.1109/VLSIT.1991.706015
Pfiester, J. R. et al. An ultra-shallow buried-channel PMOST using boron penetration. IEEE Trans. Electron Devices 40, 207–213 (1993).
Esseni, D. & Pala, M. G. Interface traps in InAs nanowire tunnel FETs and MOSFETs – part II: comparative analysis and trap induced variability. IEEE Trans. Electron Devices 60, 2802–2807 (2013).
Park, B.-G., Hwang, S. W. & Park, Y. J. in Nanoelectronic Devices 222–223 (Pan Stanford Publishing, 2012).
Asenov, A. et al. Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-μm MOSFET’s with epitaxial and δ-doped channels. IEEE Trans. Electron Devices 46, 1718–1724 (1999).
Taur, Y. et al. CMOS scaling into the nanometer regime. Proc. IEEE 85, 486–504 (1997).
Bol, D., Ambroise, R., Flandre, D. & Legat, J. Interests and limitations of technology scaling for subthreshold logic. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17, 1508–1519 (2009).
Lewis, S. H., Fetterman, H. S., Gross, G. F., Ramachandran, R. & Viswanathan, T. R. A 10-b 20-Msample/s analog-to-digital converter. IEEE J. Solid-State Circuits 27, 351–358 (1992).
Akopyan, F. et al. True north: design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip. IEEE Trans. Comput. -Aided Des. Integr. Circuits Syst. 34, 1537–1557 (2015).
This work was supported by the Samsung Research Funding & Incubation Center of Samsung Electronics under project number SRFC-TA1703-07 and by the U-K Brand Research Fund (1.180037.01) of UNIST (Ulsan National Institute of Science & Technology). The authors are grateful to foundry support for 130-nm and 90-nm CMOS technology processes.
The authors declare no competing interests.
Publisher’s note: Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
About this article
Cite this article
Jeong, J.W., Choi, Y., Kim, W. et al. Tunnelling-based ternary metal–oxide–semiconductor technology. Nat Electron 2, 307–312 (2019) doi:10.1038/s41928-019-0272-8
Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials
Applied Sciences (2019)
Nature Electronics (2019)