Skip to main content

Thank you for visiting nature.com. You are using a browser version with limited support for CSS. To obtain the best experience, we recommend you use a more up to date browser (or turn off compatibility mode in Internet Explorer). In the meantime, to ensure continued support, we are displaying the site without styles and JavaScript.

Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond

Abstract

The drive to deliver increasingly powerful and feature-rich integrated circuits has made technology node scaling—the process of reducing transistor dimensions and increasing their density in microchips—a key challenge in the microelectronics industry. Historically, advances in optical lithography patterning have played a central role in allowing this trend to continue. Directed self-assembly of block copolymers is a promising alternative patterning technique that offers sub-lithographic resolution and reduced process complexity. However, the feasibility of applying this approach to the fabrication of critical device layers in future technology nodes has never been verified. Here we compare the use of directed self-assembly and conventional patterning methods in the fabrication of 7 nanometre node FinFETs, using an industrially relevant and high-volume manufacturing-compliant test vehicle. Electrical validation shows comparable device performance, suggesting that directed self-assembly could offer a simplified patterning technique for future semiconductor technology.

Access options

Rent or Buy article

Get time limited or full article access on ReadCube.

from$8.99

All prices are NET prices.

Fig. 1: Fin patterning process flow and cost/complexity analysis.
Fig. 2: FinFET formation at different stages.
Fig. 3: Representative top-down SEM images of fins at the ‘post-fin-reveal’ stage and their characteristics.
Fig. 4: Electrical characterization of DSA and baseline devices of 24-fin NFET.
Fig. 5: Comparison of 24-fin long-channel NFET device performance using baseline process and DSA.

Data availability

The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.

References

  1. 1.

    Park, M., Harrison, C., Chaikin, P. M., Register, R. A. & Adamson, D. H. Block copolymer lithography: periodic arrays of~1011 holes in 1 square centimeter. Science 276, 1401–1404 (1997).

    Article  Google Scholar 

  2. 2.

    Black, C. T. et al. Polymer self assembly in semiconductor microelectronics. IBM J. Res. Dev. 51, 605–633 (2007).

    Article  Google Scholar 

  3. 3.

    Thurn-Albrecht, T. et al. Ultrahigh-density nanowire arrays grown in self-assembled diblock copolymer templates. Science 290, 2126–2129 (2000).

    Article  Google Scholar 

  4. 4.

    Segalman, R. A., Yokoyama, H. & Kramer, E. J. Graphoepitaxy of spherical domain block copolymer films. Adv. Mater. 13, 1152–1155 (2001).

    Article  Google Scholar 

  5. 5.

    Bita, I. et al. Graphoepitaxy of self-assembled block copolymers on two-dimensional periodic patterned templates. Science 321, 939–943 (2008).

    Article  Google Scholar 

  6. 6.

    Kim, S. O. et al. Epitaxial self-assembly of block copolymers on lithographically defined nanopatterned substrates. Nature 424, 411–414 (2003).

    Article  Google Scholar 

  7. 7.

    Stoykovich, M. P. et al. Directed assembly of block copolymer blends into nonregular device-oriented structures. Science 308, 1442–1446 (2005).

    Article  Google Scholar 

  8. 8.

    Albrecht, T. R. et al. Bit-patterned magnetic recording: Theory, media fabrication, and recording performance. IEEE Trans. Magn. 51, 1–42 (2015).

    Article  Google Scholar 

  9. 9.

    Liu, C.-C. et al. DSA patterning options for logic and memory applications. Proc. SPIE 10146, 1014603 (2017).

  10. 10.

    Tsai, H. et al. Two-dimensional pattern formation using graphoepitaxy of PS-b-PMMA block copolymers for advanced FinFET device and circuit fabrication. ACS Nano 8, 5227–5232 (2014).

    Article  Google Scholar 

  11. 11.

    Black, C. et al. Integration of self-assembled diblock copolymers for semiconductor capacitor fabrication. Appl. Phys. Lett. 79, 409–411 (2001).

    Article  Google Scholar 

  12. 12.

    Ruiz, R. et al. Density multiplication and improved lithography by directed block copolymer assembly. Science 321, 936–939 (2008).

    Article  Google Scholar 

  13. 13.

    Hong, A. J. et al. Metal nanodot memory by self-assembled block copolymer lift-off. Nano. Lett. 10, 224–229 (2010).

    Article  Google Scholar 

  14. 14.

    Muramatsu, M. et al. Pattern defect reduction and LER improvement of chemo-epitaxy DSA process. Proc. SPIE 10144, 101440Q (2017).

  15. 15.

    Pathangi, H. et al. Defect mitigation and root cause studies in 14 nm half-pitch chemo-epitaxy directed self-assembly LiNe flow. J. Micro/Nanolith. MEMS MOEMS 14, 031204 (2015).

    Article  Google Scholar 

  16. 16.

    Azuma, T. et al. Electrical yield verification of half-pitch 15 nm patterns using directed self-assembly of polystyrene-block-poly (methyl methacrylate). J. Vac. Sci. Technol. B 33, 06F302 (2015).

    Article  Google Scholar 

  17. 17.

    Mitra, J., Torres, A. & Pan, D. Z. Process, design rule, and layout co-optimization for DSA based patterning of sub-10 nm FinFET devices. Proc. SPIE 10144, 101440G (2017).

  18. 18.

    Jacob, A. P. et al. Scaling challenges for advanced CMOS devices. Int. J. High Speed Electron. Syst. 26, 1740001 (2017).

    Article  Google Scholar 

  19. 19.

    Xie, R. et al. A 7 nm FinFET technology featuring EUV patterning and dual strained high mobility channels. In 2016 IEEE Int. Electron Devices Meet. (IEDM) 2.7.1–2.7.4 (IEEE, 2017)

  20. 20.

    Liu, C.-C. et al. Chemical patterns for directed self-assembly of lamellae-forming block copolymers with density multiplication of features. Macromolecules 46, 1415–1424 (2013).

    Article  Google Scholar 

  21. 21.

    Xu, P. et al. Sidewall spacer quadruple patterning for 15 nm half-pitch. Proc. SPIE 7973, 79731Q (2011).

  22. 22.

    Oyama, K. et al. Sustainability and applicability of spacer-related patterning towards 7 nm node. Proc. SPIE 9425, 942514 (2015).

  23. 23.

    Suh, H. S. et al. Sub-10-nm patterning via directed self-assembly of block copolymer films with a vapour-phase deposited topcoat. Nat. Nanotech. 12, 575–581 (2017).

    Article  Google Scholar 

  24. 24.

    Lane, A. P. et al. Directed self-assembly and pattern transfer of five nanometer block copolymer lamellae. ACS Nano 11, 7656–7665 (2017).

    Article  Google Scholar 

  25. 25.

    Wan, L. et al. The limits of lamellae-forming PS-b-PMMA block copolymers for lithography. ACS Nano 9, 7506–7514 (2015).

    Article  Google Scholar 

  26. 26.

    Pathangi, H. et al. Improved cost-effectiveness of the block co-polymer anneal process for DSA. Proc. SPIE 9777, 97771Z (2016).

  27. 27.

    Markoff, J. IBM discloses working version of a much higher-capacity chip. The New York Times (9 July 2015).

  28. 28.

    Ha, D. et al. Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications. In 2017 Symp. VLSI Tech. (VLSIT) T68–T69 (IEEE, 2017).

  29. 29.

    Wu, S. et al. A 7 nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027μm 2 high density 6-T SRAM cell for mobile SoC applications. In 2016 IEEE Int. Electron Devices Meet. (IEDM) 2.6.1–2.6.4 (IEEE, 2016).

  30. 30.

    Auth, C. et al. A 10 nm high performance and low-power CMOS technology. In 2017 IEEE Int. Electron Devices Meet. (IEDM) 29.21.21–29.21.24 (IEEE, 2017).

  31. 31.

    Gunay-Demirkol, A. et al. Innovative scatterometry approach for self-aligned quadruple patterning (SAQP) process control. Proc. SPIE 9778, 977807 (2016).

    Article  Google Scholar 

  32. 32.

    Lorusso, G. F. et al. Enabling CD SEM metrology for 5 nm technology node and beyond. Proc. SPIE 10145, 1014512 (2017).

    Article  Google Scholar 

  33. 33.

    Kato, T. et al. Advanced CD-SEM metrology for pattern roughness and local placement of lamellar DSA. SPIE Proc 9050, 90501T (2014).

    Article  Google Scholar 

  34. 34.

    Gogolides, E., Constantoudis, V. & Kokkoris, G. Towards an integrated line edge roughness understanding: metrology, characterization, and plasma etching transfer. Proc. SPIE 8685, 868505 (2013).

    Article  Google Scholar 

  35. 35.

    Lin, C.-H. et al. Modeling of width-quantization-induced variations in logic FinFETs for 22 nm and beyond. In 2011 Symp. VLSI Tech. (VLSIT) 16–17 (IEEE, 2011).

  36. 36.

    Liu, C.-C. et al. DSA patterning options for FinFET formation at 7 nm node. Proc. SPIE 9777, 97770R (2016).

    Article  Google Scholar 

  37. 37.

    Gronheid, R. et al. Defect reduction and defect stability in IMEC’s 14 nm half-pitch chemo-epitaxy DSA flow. Proc. SPIE 9049, 904905 (2014).

    Article  Google Scholar 

Download references

Acknowledgements

The authors would like to thank M. Colburn, M. Guillorn, S. Sieg, D. Sanders, J. Arnold, S. Burns, R. Allen, J. Pitera, R. Divakaruni, M. Khare and T. C. Chen for their technical and/or management support. The authors are grateful for all the support from their colleagues at IBM Albany NanoTech, including Alliance partners, IBM Almaden Research Center and IBM T. J. Watson Research Center. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities. Experimental materials used in this work were purchased from or provided by AZ (now EMD, a subsidiary of Merck) and JSR Micro, and greatly appreciated by the authors.

Author information

Affiliations

Authors

Contributions

C.-C.L. conceived and designed the experiments. E.F., Y.M., R.X., C.C., R.F. and C.-C.L. performed the material characterization, device fabrication and electron microscope image analysis. K.L. performed the device layout and optical proximity correction (OPC)-related analysis. C.W.Y., J.Z., C.Z and C.-C.L. performed the device measurements and data analysis. C.-C.L., H.T. and R.F. wrote the manuscript. All authors discussed the results and commented on the manuscript.

Corresponding author

Correspondence to Chi-Chun Liu.

Ethics declarations

Competing interests

The authors declare no competing interests.

Additional information

Publisher’s note: Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Supplementary information

Supplementary Information

Supplementary Notes 1–3, Supplementary Figures 1–3, and Supplementary Tables 1–3

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Liu, CC., Franke, E., Mignot, Y. et al. Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond. Nat Electron 1, 562–569 (2018). https://doi.org/10.1038/s41928-018-0147-4

Download citation

Further reading

Search

Quick links

Nature Briefing

Sign up for the Nature Briefing newsletter — what matters in science, free to your inbox daily.

Get the most important science stories of the day, free in your inbox. Sign up for Nature Briefing