IEEE J. Solid-State Circuits https://doi.org/10.1109/JSSC.2018.2863950 (2018)

The next mobile telecommunications standard — often referred to as 5G — is expected to roll out around 2020. 5G targets peak data rates of 10 Gbit s–1 (ten times faster than 4G), latency (the time between command and action) of 1 ms and connection densities of 106 devices km–2. The upcoming deployment of 5G has generated significant excitement because such low latencies could, for example, enable responsive control of remote robots or vehicles, and communications channels capable of supporting a high density of connected devices is a key prerequisite for the Internet of Things (IoT).

Developing a digital communications scheme that can handle a large number of users, and large amounts of data, in an energy- and memory-efficient manner is a key challenge for devices using 5G technology. Byeong Yong Kong and In-Cheol Park at the Korea Advanced Institute of Science and Technology now report a digital communications architecture based on a modified interleave division multiple access (IDMA) scheme to achieve savings in memory utilization, device area and power consumption. In typical IDMA schemes there are two steps that occur in sequence: the first is data storage, the second is data processing and storage of the processed data. Here, the researchers have instead skipped the first step (storing raw data) and directly processed the data and stored the results ‘on the-fly’. Compared to the latest low-latency architecture, their approach reduces the memory requirement by 43%, occupies 61% less silicon area and consumes 70% less power on average.