In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques.
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S.S., K.N. and S.D. acknowledge funding from ASCENT, one of six centres in JUMP (Joint University Microelectronics Program), a Semiconductor Research Corporation (S.R.C.) program sponsored by DARPA.
The authors declare no competing interests.
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Salahuddin, S., Ni, K. & Datta, S. The era of hyper-scaling in electronics. Nat Electron 1, 442–450 (2018). https://doi.org/10.1038/s41928-018-0117-x
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