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Resistive random-access memory based on ratioed memristors

Nature Electronics volume 1, pages 466–472 (2018)Cite this article

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Abstract

Resistive random-access memories made from memristor crossbar arrays could provide the next generation of non-volatile memories. However, integrating large memristor crossbar arrays is challenging due to the high power consumption that originates from leakage currents (known as the sneak-path problem) and the large device-to-device and cycle-to-cycle variations of memristors. Here we report a memory cell comprised of two serially connected memristors and a minimum-sized transistor. With this approach, we use the ratio of the resistances of the memristors to encode information, rather than the absolute resistance of a single memristor, as is traditionally used in resistive-based memories. The minimum-sized transistor, which is connected to the midpoint between the two series-connected memristors, is used to sense the voltage to read the state of the cell and to assist with write operations. Our memory cell design solves the sneak-path problem and, compared to the traditional resistance-based current sensing approach for memory reads, our ratio-based voltage sensing scheme is more robust and less prone to data errors caused by variations in memristors.

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Fig. 1: Bipolar memristor characteristics, the crossbar architecture and its parasitic currents.
Fig. 2: The H3 cell, its array architecture and proposed 6F2 layout.
Fig. 3: Demonstration of the degree of variations in memristors and their reduction using our ratio-based voltage sensing approach.
Fig. 4: Unsupervised pulse programming comparison between the resistance-based and ratio-based sensing approaches.
Fig. 5: Comparison of the error probability between the resistance-based and ratio-based approaches.
Fig. 6: mFET-assisted write evaluation.

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Acknowledgements

The authors would like to thank D. Strukov and his research group for providing the memristors used in this paper and the procedure to electroform and program them.

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Authors and Affiliations

  1. Electrical and Computer Engineering Department, University of California Santa Barbara, Santa Barbara, CA, USA

    Miguel Angel Lastras-Montaño

  2. School of Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kawloon, Hong Kong

    Kwang-Ting Cheng

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  1. Miguel Angel Lastras-Montaño
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  2. Kwang-Ting Cheng
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Contributions

M.A.L.-M. conceived the initial idea, conducted the measurements and analysed the results. K.-T.C. supervised the research, discussed the idea and results, and suggested actions throughout the research. M.A.L.-M. and K.-T.C. wrote the manuscript and discussed the results and implications at all stages.

Corresponding authors

Correspondence to Miguel Angel Lastras-Montaño or Kwang-Ting Cheng.

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A patent application has been submitted by HKUST and UCSB based on these results.

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Supplementary Information

Supplementary Notes 1–8 and Supplementary Figures 1–8

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Lastras-Montaño, M.A., Cheng, KT. Resistive random-access memory based on ratioed memristors. Nat Electron 1, 466–472 (2018). https://doi.org/10.1038/s41928-018-0115-z

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