Modern computers are based on the von Neumann architecture in which computation and storage are physically separated: data are fetched from the memory unit, shuttled to the processing unit (where computation takes place) and then shuttled back to the memory unit to be stored. The rate at which data can be transferred between the processing unit and the memory unit represents a fundamental limitation of modern computers, known as the memory wall. In-memory computing is an approach that attempts to address this issue by designing systems that compute within the memory, thus eliminating the energy-intensive and time-consuming data movement that plagues current designs. Here we review the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, their resistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation. We examine the different digital, analogue, and stochastic computing schemes that have been proposed, and explore the microscopic physical mechanisms involved. Finally, we discuss the challenges in-memory computing faces, including the required scaling characteristics, in delivering next-generation computing.
Subscribe to Journal
Get full journal access for 1 year
only $8.25 per issue
All prices are NET prices.
VAT will be added later in the checkout.
Tax calculation will be finalised during checkout.
Rent or Buy article
Get time limited or full article access on ReadCube.
All prices are NET prices.
Moore, G. E. Cramming more components onto integrated circuits. Electronics 38, 114–117 (1965).
Waldrop, M. M. The chips are down for Moore’s law. Nature 530, 144–147 (2016).
Wulf, W. A. & McKee, S. A. Hitting the memory wall: implications of the obvious. ACM SIGARCH Computer Architecture News 23, 20–24 (1995).
Horowitz, M. Computing’s energy problem (and what we can do about it). 2014 IEEE Int. Solid-State Circuits Conf. Digest Tech. Papers (ISSCC) https://doi.org/10.1109/ISSCC.2014.6757323 (2014). This work reviews the power limitation of modern computers, highlighting the importance of application-optimized computing to improve the energy efficiency.
Chen, Y.-H., Krishna, T., Emer, J. S. & Sze, V. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE J. Solid-State Circuits 52, 127–138 (2017).
Jouppi, N. P. et al. In-datacenter performance analysis of a tensor processing unit. Proc. 44th Int. Symp. Comp. Architecture (ISCA) https://doi.org/10.1145/3079856.3080246 (2017).
Pawlowski, J. T. Hybrid memory cube (HMC). 2011 IEEE Hot Chips 23 Symp. (HCS) https://doi.org/10.1109/HOTCHIPS.2011.7477494 (2011).
Lee, D. U. et al. A 1.2 V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29 nm process and TSV. 2014 IEEE Int. Solid-State Circuits Conf. Digest Tech. Papers (ISSCC) https://doi.org/10.1109/ISSCC.2014.6757501 (2014).
Wong, H.-S. P. & Salahuddin, S. Memory leads the way to better computing. Nat. Nanotech. 10, 191–194 (2015).
Waser, R. & Aono, M. Nanoionics-based resistive switching memories. Nat. Mater. 6, 833–840 (2007).This is the first review on resistive switching memory describing the physical mechanisms and the experimental techniques to investigate them.
Raoux, S., Welnic, W. & Ielmini, D. Phase change materials and their application to non-volatile memories. Chem. Rev. 110, 240–267 (2010).
Kent, A. D. & Worledge, D. C. A new spin on magnetic memories. Nat. Nanotech. 10, 187–191 (2015).
Mikolajick, T. et al. FeRAM technology for high density applications. Microelectron. Reliab. 41, 947–950 (2001).
Di Ventra, M. & Pershin, Y. V. The parallel approach. Nat. Phys. 9, 200–202 (2013).
Indiveri, G. & Liu, S.-C. Memory and information processing in neuromorphic systems. Proc. IEEE 103, 1379–1397 (2015).
Beck, A., Bednorz, J. G., Gerber, Ch., Rossel, C. & Widmer, D. Reproducible switching effect in thin oxide films for memory applications. Appl. Phys. Lett. 77, 139 (2000).This is the first work demonstrating reproducible resistance switching in an oxide layer, thus paving the way for memory applications.
Liu, Q. et al. Real-time observation on dynamic growth/dissolution of conductive filaments in oxide-electrolyte-based ReRAM. Adv. Mater. 24, 1844–1849 (2012).
Ielmini, D. Modeling the universal set/reset characteristics of bipolar RRAM by field- and temperature-driven filament growth. IEEE Trans. Electron Devices 58, 4309–4317 (2011).
Yang, J. J., Strukov, D. B. & Stewart, D. R. Memristive devices for computing. Nat. Nanotech. 8, 13–24 (2013).
Kim, K. M., Jeong, D. S. & Hwang, C. S. Nanofilamentary resistive switching in binary oxide system; a review on the present status and outlook. Nanotechnology 22, 254002 (2011).
Sawa, A. Resistive switching in transition metal oxides. Mater. Today 11, 28–36 (2008).
Yamada, N., Ohno, E., Nishiuchi, K. & Akahira, N. Rapid‐phase transitions of GeTe‐Sb2Te3 pseudobinary amorphous thin films for an optical disk memory. J. Appl. Phys. 69, 2849 (1991).
Ielmini, D. & Zhang, Y. Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices. J. Appl. Phys. 102, 054517 (2007).
Boniardi, M. et al. Optimization metrics for phase change memory (PCM) cell architectures. 2014 IEEE Int. Electron Devices Meet. (IEDM) https://doi.org/10.1109/IEDM.2014.7047131 (2014).
Choi, B. J. et al. High‐speed and low‐energy nitride memristors. Adv. Funct. Mater. 26, 5290–5296 (2016).
Loke, D. et al. Breaking the speed limits of phase-change memory. Science 336, 1566–1569 (2012).
Lee, M.-J. et al. A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5−x/TaO2−x bilayer structures. Nat. Mater. 10, 625–630 (2011).
Chappert, C., Fert, A. & Nguyen Van Dau, F. The emergence of spin electronics in data storage. Nat. Mater. 6, 813–823 (2007).
Locatelli, N., Cros, V. & Grollier, J. Spin-torque building blocks. Nat. Mater. 13, 11–20 (2014).
Slonczewski, J. Current-driven excitation of magnetic multilayers. J. Magn. Magn. Mater. 159, L1–L7 (1996).This work theoretically predicted spin transfer torque, where the magnetic polarization in a ferromagnetic layer can be switched by a current of spin-polarized electrons.
Yuasa, S., Nagahama, T., Fukushima, A., Suzuki, Y. & Ando, K. Giant room-temperature magnetoresistance in single-crystal Fe/MgO/Fe magnetic tunnel junctions. Nat. Mater. 3, 868–871 (2004).
Carboni, R. et al. Understanding cycling endurance in perpendicular spin-transfer torque (p-STT) magnetic memory. 2016 IEEE Int. Electron Devices Meet. (IEDM) https://doi.org/10.1109/IEDM.2016.7838468 (2016).
Boescke, T. S., Mueller, J., Brauhaus, D., Schroeder, U. & Boettger, U. Ferroelectricity in hafnium oxide thin films. Appl. Phys. Lett. 99, 102903 (2011).
Trentzsch, M. et al. A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs. 2016 IEEE Int. Electron Devices Meet. (IEDM) https://doi.org/10.1109/IEDM.2016.7838397 (2016).
Oh, S. et al. HfZrOx -based ferroelectric synapse device with 32 levels of conductance states for neuromorphic applications. IEEE Electron Device Lett. 38, 732–735 (2017).
Niemier, M. T. et al. Nanomagnet logic: progress toward system-level integration. J. Phys. Condens. Matter 23, 493202 (2011).
Amlani, I. et al. Digital logic gate using quantum-dot cellular automata. Science 284, 289–291 (1999).
Khajetoorians, A. A., Wiebe, J., Chilian, B. & Wiesendanger, R. Realizing all-spin-based logic operations atom by atom. Science 332, 1062–1064 (2011).
Govoreanu, B. et al. 10 × 10 nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation. 2011 Int. Electron Devices Meet. (IEDM) https://doi.org/10.1109/IEDM.2011.6131652 (2011). This is the first work demonstrating the scalability of RRAM in the lateral size range of 10 nm.
Linn, E., Rosezin, R., Tappertzhofen, S., Böttger, U. & Waser, R. Beyond von Neumann—logic operations in passive crossbar arrays alongside memory operations. Nanotechnology 23, 305205 (2012).
Gaillardon, P.-E. et al. The programmable logic-in-memory (PLiM) computer. IEEE Design, Automation & Test in Europe Conference (DATE) 427–432 (2016); https://infoscience.epfl.ch/record/213465/files/PEG_DATE16.pdf
Papandroulidakis, G., Vourkas, I., Vasileiadis, N. & Sirakoulis, G. Ch. Boolean logic operations and computing circuits based on memristors. IEEE Trans. Circuits Syst. II: Express Briefs 61, 972–976 (2014).
Nikonov, D. E. & Young, I. A. Overview of beyond-CMOS devices and a uniform methodology for their benchmarking. Proc. IEEE 101, 2498–2533 (2013).
Gao, L., Alibart, F. & Strukov, D. B. Programmable CMOS/memristor threshold logic. IEEE Trans. Nanotechnology 12, 115–119 (2013).
James, A. P., Francis, L. R. V. J. & Kumar, D. S. Resistive threshold logic. IEEE Trans. Very Large Scale Integr. (VLSI) 22, 190–195 (2014).
Borghetti, J. et al. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature 464, 873–876 (2010).This is the first work proposing the idea of stateful Boolean operation with RRAM, where memory devices are used for digital computation.
Reuben, J. et al. Memristive logic: A framework for evaluation and comparison. 27th Int. Symp. Power and Timing Modeling, Optimization and Simulation (PATMOS) https://doi.org/10.1109/PATMOS.2017.8106959 (2017).
Jeong, D. S., Kim, K. M., Kim, S., Choi, B. J. & Hwang, C. S. Memristors for energy-efficient new computing paradigms. Adv. Electron. Mater. 2, 1600090 (2016).
Balatti, S., Ambrogio, S. & Ielmini, D. Normally-off logic based on resistive switches—Part I: Logic gates. IEEE Trans. Electron Devices 62, 1831–1838 (2015).
Huang, P. et al. Reconfigurable non-volatile logic operations in resistance switching crossbar array for large-scale circuits. Adv. Mater. 28, 9758–9764 (2016).
Chen, B. et al. Efficient in-memory computing architecture based on crossbar arrays. 2015 IEEE Int. Electron Devices Meet. (IEDM) https://doi.org/10.1109/IEDM.2015.7409720 (2015).
Cassinerio, M., Ciocchini, N. & Ielmini, D. Logic computation in phase change materials by threshold and memory switching. Adv. Mater. 25, 5975–5980 (2013).
Mahmoudi, H., Windbacher, T., Sverdlov, V. & Selberherr, S. Implication logic gates using spin-transfer-torque-operated magnetic tunnel junctions for intrinsic logic-in-memory. Solid-State Electron. 84, 191–197 (2013).
Balatti, S. et al. Voltage-controlled cycling endurance of HfOx-based resistive-switching memory (RRAM). IEEE Trans. Electron Devices 62, 3365–3372 (2015).
Clark, L. T. et al. ASAP7: A 7-nm FinFET predictive process design kit. Microelectron. J. 53, 105–115 (2016).
Wright, C. D., Hosseini, P. & Vazquez Diosdado, J. A. Beyond von-Neumann computing with nanoscale phase-change memory devices. Adv. Funct. Mater. 23, 2248–2254 (2013).This is the first work proposing the use of cumulative crystallization in PCM as a means for analogue computation and neuron-like integration.
Feldmann, J. et al. Calculating with light using a chip-scale all-optical abacus. Nat. Commun. 8, 1256 (2017).
Hosseini, P., Sebastian, A., Papandreou, N., Wright, C. D. & Bhaskaran, H. Accumulation-based computing using phase-change memories with FET access devices. IEEE Electron Device Lett. 36, 975–977 (2015).
Bichler, O. et al. Visual pattern extraction using energy-efficient 2-PCM synapse neuromorphic architecture. IEEE Trans. Electron Devices 59, 2206–2214 (2012).
Burr, G. W. et al. Experimental demonstration and tolerancing of a large-scale neural network (165 000 synapses) using phase-change memory as the synaptic weight element. IEEE Trans. Electron Devices 62, 3498–3507 (2015).
Tuma, T., Pantazi, A., Le Gallo, M., Sebastian, A. & Eleftheriou, E. Stochastic phase-change neurons. Nat. Nanotech. 11, 693–699 (2016).
Qiao, N. & Indiveri, G. Scaling mixed-signal neuromorphic processors to 28 nm FD-SOI technologies. IEEE Biomedical Circuits & Systems Conference (BioCAS) https://doi.org/10.1109/BioCAS.2016.7833854 (2016).
Stoliar, P. et al. A leaky‐integrate-and-fire neuron analog realized with a Mott insulator. Adv. Funct. Mater. 27, 1604740 (2017).
Wang, Z. et al. Fully memristive neural networks for pattern classification with unsupervised learning. Nat. Electron 1, 137–145 (2018).
Larentis, S., Nardi, F., Balatti, S., Gilmer, D. C. & Ielmini, D. Resistive switching by voltage-driven ion migration in bipolar RRAM—Part II: Modeling. IEEE Trans. Electron Devices 59, 2468–2475 (2012).
Yu, S., Wu, Y., Jeyasingh, R., Kuzum, D. & Wong, H.-S. P. An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation. IEEE Trans. Electron Devices 58, 2729–2737 (2011).
Yu, S. et al. A low energy oxide-based electronic synaptic device for neuromorphic visual systems with tolerance to device variation. Adv. Mater. 25, 1774–1779 (2013).
Prezioso, M. et al. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 521, 61–64 (2015).
Jang, J.-W., Park, S., Burr, G. W., Hwang, H. & Jeong, Y.-H. Optimization of conductance change in Pr1−xCa x MnO3-based synaptic devices for neuromorphic systems. IEEE Electron Device Lett 36, 457–459 (2015).
Chanthbouala, A. et al. A ferroelectric memristor. Nat. Mater. 11, 860–864 (2012).
Lequeux, S. et al. A magnetic synapse: multilevel spin-torque memristor with perpendicular anisotropy. Sci. Rep. 6, 31510 (2016).
Diorio, C., Hasler, P., Minch, B. A., & Mead, C. A single-transistor silicon synapse. IEEE Trans. Electron Devices 43, 1972–1980 (1996).This is the first work proposing the adoption of a flash memory as a synapse capable of plasticity by weight update.
Ambrogio, S. et al. Statistical fluctuations in HfO x resistive-switching memory (RRAM): Part I—Set/reset variability. IEEE Trans. Electron Devices 61, 2912–2919 (2014).
Rizzi, M. et al. Cell-to-cell and cycle-to-cycle retention statistics in phase-change memory arrays. IEEE Trans. Electron Devices 62, 2205–2211 (2015).
Chen, A. Utilizing the variability of resistive random access memory to implement reconfigurable physical unclonable functions. IEEE Electron Device Lett. 36, 138–140 (2015).
Herder, C., Yu, M.-D., Koushanfar, F. & Devadas, S. Physical unclonable functions and applications: A tutorial. Proc. IEEE 102, 1126–1141 (2014).
Maass, W. Noise as a resource for computation and learning in networks of spiking neurons. Proc. IEEE 102, 860–880 (2014).
Jun, B. & Kocher, P. The Intel Random Number Generator (Rambus, 1999); https://www.rambus.com/intel-random-number-generator/
Ambrogio, S. et al. Statistical fluctuations in HfO x resistive-switching memory (RRAM): Part II—Random telegraph noise. IEEE Trans. Electron Devices 61, 2920–2927 (2014).
Huang, C.-Y., Shen, W. C., Tseng, Y.-H., King, Y.-C. & Lin, C.-J. A contact-resistive random-access-memory-based true random number generator. IEEE Electron Device Lett. 33, 1108–1110 (2012).
Jiang, H. et al. A novel true random number generator based on a stochastic diffusive memristor. Nat. Commun. 8, 882 (2017).
Balatti, S., Ambrogio, S., Wang, Z.-Q. & Ielmini, D. True random number generation by variability of resistive switching in oxide-based devices. IEEE J. Emerging Topics in Circuits and Systems (JETCAS) 5, 214–221 (2015).
Gaba, S., Sheridan, P., Zhou, J., Choi, S. & Lu, W. Stochastic memristive devices for computing and neuromorphic applications. Nanoscale 5, 5872 (2013).
Choi, W. H. et al. A magnetic tunnel junction based true random number generator with conditional perturb and real-time output probability tracking. 2014 IEEE Int. Electron Devices Meet. (IEDM) https://doi.org/10.1109/IEDM.2014.7047039 (2014).
Fukushima, A. et al. Spin dice: A scalable truly random number generator based on spintronics. Appl. Phys. Express 7, 083001 (2014).
Balatti, S. et al. Physical unbiased generation of random numbers with coupled resistive switching devices. IEEE Trans. Electron Devices 63, 2029–2035 (2016).
Jo, S. H., Kim, K.-H. & Lu, W. High-density crossbar arrays based on a Si memristive system. Nano Lett. 9, 870–874 (2009).
Kau, D. et al. A stackable cross point phase change memory. 2009 IEEE Int. Electron Devices Meet. (IEDM) https://doi.org/10.1109/IEDM.2009.5424263 (2009).
Truong, S. N. & Min, K.-S. New memristor-based crossbar array architecture with 50-% area reduction and 48-% power saving for matrix-vector multiplication of analog neuromorphic computing. J. Semicond. Technol. Sci. 14, 356–363 (2014).
Li, C. et al. Analogue signal and image processing with large memristor crossbars. Nat. Electron 1, 52–59 (2018).
Eryilmaz, S. B. Brain-inspired and Non-conventional Computing with Emerging Memory Devices PhD thesis, Stanford University (2017); https://searchworks.stanford.edu/view/12137356
Sheridan, P. M. et al. Sparse coding with memristor networks. Nat. Nanotech. 12, 784–789 (2017).
Gao, L., Chen, P.-Y., Liu, R. & Yu, S. Physical unclonable function exploiting sneak paths in resistive cross-point array. IEEE Trans. Electron Devices 63, 3109–3115 (2016).
Ielmini, D., Lacaita, A. L. & Mantegazza, D. Recovery and drift dynamics of resistance and threshold voltages in phase change memories. IEEE Trans. Electron Devices 54, 308–315 (2007).
Ielmini, D., Sharma, D., Lavizzari, S. & Lacaita, A. L. Reliability impact of chalcogenide-structure relaxation in phase change memory (PCM) cells—Part I: Experimental study. IEEE Trans. Electron Devices 56, 1070–1077 (2009).
Kim, S. et al. A phase change memory cell with metallic surfactant layer as a resistance drift stabilizer. 2013 IEEE Int. Electron Devices Meet. (IEDM) https://doi.org/10.1109/IEDM.2013.6724727 (2013).
Daly, D. C., Fujino, L. C. & Smith, K. C. Through the looking glass — The 2017 edition: Trends in solid-state circuits from ISSCC. IEEE Solid-State Circuits Mag. 9, 12–22 (2017).
Kapur, P., McVittie, J. P. & Saraswat, K. C. Technology and reliability constrained future copper interconnects—Part I: Resistance modeling. IEEE Trans. Electron Devices 49, 590–597 (2002).
Geim, A. K. & Novoselov, K. S. The rise of graphene. Nat. Mater. 6, 183–191 (2007).
Yu, S., Chen, H.-Y., Gao, B., Kang, J. & Wong, H.-S. P. HfO x based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional cross-point architecture. ACS Nano 7, 2320 (2013).
Li, H., Wu, T. F., Mitra, S. & Wong, H.-S. P. Resistive RAM-centric computing: Design and modeling methodology. IEEE Trans. Circuits and Systems I: Regular Papers 64, 2263–2273 (2017).
D.I. acknowledges funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation programme (grant agreement no. 648635). H.-S.P.W. is supported in part by DARPA, the National Science Foundation (E2CDA, Expeditions in Computing), in addition to member companies of: Stanford Non-Volatile Memory Technology Research Initiative (NMTRI) and Stanford SystemX Alliance.
The authors declare no competing interests.
Publisher's note: Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
About this article
Cite this article
Ielmini, D., Wong, HS.P. In-memory computing with resistive switching devices. Nat Electron 1, 333–343 (2018). https://doi.org/10.1038/s41928-018-0092-2
In materia reservoir computing with a fully memristive architecture based on self-organizing nanowire networks
Nature Materials (2021)
Investigation of switching uniformity in resistive memory via finite element simulation of conductive-filament formation
Scientific Reports (2021)
Nature Communications (2021)
Scientific Reports (2021)