Holography is a method of recording and reproducing three-dimensional (3D) images, and the widespread availability of computers has encouraged the development of holographic 3D screens (electroholography). However, the technology has not yet been used in practical applications because a hologram requires an enormous volume of data and modern computing power is inadequate to process this volume of data in real time. Here, we show that a special-purpose holography computing board, which uses eight large-scale field-programmable gate arrays, can be used to generate 108-pixel holograms that can be updated at a video frame rate. With our approach, we achieve a parallel operation of 4,480 hologram calculation circuits on a single board, and by clustering eight of these boards, we can increase the number of parallel calculations to 35,840. Using a 3D image composed of 7,877 points, we show that 108-pixel holograms can be updated at a video rate, thus allowing 3D movies to be projected. We also demonstrate that the system speed scales up in a linear manner as the number of parallel circuits is increased. The system operates at 0.25 GHz with an effective speed equivalent to 0.5 petaflops (1015 floating-point operations per second), matching that of a high-performance computer.

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This work was supported by the Japan Society for the Promotion of Science (Grant-in-Aid No. 25240015).

Author information


  1. Chiba University, Chiba, Japan

    • Takashige Sugie
    • , Takanori Akamatsu
    • , Takashi Nishitsuji
    • , Ryuji Hirayama
    • , Atsushi Shiraki
    • , Yutaka Endo
    • , Takashi Kakue
    • , Tomoyoshi Shimobaba
    •  & Tomoyoshi Ito
  2. Tokyo University of Science, Tokyo, Japan

    • Nobuyuki Masuda
  3. National Astronomical Observatory of Japan, Mitaka, Japan

    • Hirotaka Nakayama
  4. National Institute of Information and Communications Technology, Koganei, Japan

    • Yasuyuki Ichihashi
  5. Kochi University, Kochi, Japan

    • Minoru Oikawa
    •  & Naoki Takada


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T.I. planed the project. T.Sugie and T.I designed the HORN-8 board, and T.Sugie and M.O. developed it. T.A., T.Sugie and T.I. designed the circuit of the HORN-8 system, and T.A. implemented it to FPGA. R.H., H.N., T.Sugie, T.A, T.Shimobaba and T.I. evaluated the HORN-8 system. H.N. and R.H. created 3D models for holography. T.N., N.T., Y.E., N.M. and T.Shimobaba developed the supported algorithms for the HORN-8 system. Y.I., A.S. and T.K. built the optical system. All authors contributed to the discussions and reviewed the manuscript.

Competing interests

The authors declare no competing interests.

Corresponding author

Correspondence to Tomoyoshi Ito.

Supplementary information

  1. Supplementary Video 1

    Real-time optical reconstruction of electroholography from the eight-board HORN-8 cluster system. The image was reconstructed from a 2-million-pixel hologram with 6.5-μm pixel pitch.

  2. Supplementary Video 2

    Simulation of a wide field-of-view electroholography from the eight-board HORN-8 cluster system. The image was computationally reconstructed from a 100-million-pixel hologram with 1-μm pixel pitch. The viewing angle of the hologram is approximately 30°.

  3. Supplementary Video 3

    Large-scale electroholographic image obtained using the eight-board HORN-8 cluster system. A 100-million-pixel hologram was generated from a 10-million-point object and reconstructed via simulation. The object data were divided into 160 blocks, and a separate hologram was prepared for each. These were then reconstructed by the time-division method to obtain a single still image.

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