Analogue computing based on memristors could offer a faster and more energy-efficient alternative to conventional digital computing in IoT applications.
We live in an analogue world, where the information around us is best represented by analogue parameters. Traditional computing technologies, in contrast, operate predominantly in the digital domain. This means that processing analogue signals is inefficient in terms of speed and energy consumption, as the analogue information must be converted to digital data. In the near future, these problems are likely to be exacerbated as the development of the Internet of Things (IoT) leads to the proliferation of devices whose vast amounts of generated data must be processed at the source — commonly known as ‘edge’ computing. Future conventional edge devices are expected to be connected to sensors or actuators but have limited processing power, which presents difficulties when processing real-time data with high speed and low energy consumption. New technologies and approaches are therefore required to process analogue signals. Writing in Nature Electronics, John Paul Strachan, J. Joshua Yang, Qiangfei Xia and colleagues show that large-scale memristor arrays can be used for efficient analogue computing in specific cases1.
Memristors2,3,4 are non-volatile devices whose conductance can be modulated continuously by applying a voltage. The precision in the modulation of a memristor is defined by the number of reliable conductance states within its dynamic switching window. A reconfigurable weight array, in which each cell’s conductance could be changed to different values, can be constructed using multilevel memristors, and, by virtue of Ohm’s law and Kirchhoff’s current law, such a memristor array naturally implements analogue vector and matrix multiplication. Vector-matrix multiplication operations are widely used in signal processing and deep neural networks, which are fundamental for edge computing. One way to implement analogue computing is to use the amplitudes of voltage pulses to represent input analogue signals. The result of an analogue vector-matrix multiplication is represented by the output currents, which are sensed immediately by periphery circuits. Furthermore, increasing the number of inputs has little impact on the computing speed because the multiplication is conducted in parallel. This computing process can be executed with high speed and low power, without the need to convert signals between analogue and digital format.
The researchers — who are based at the University of Massachusetts Amherst, Hewlett Packard Labs of Hewlett Packard Enterprise, HP Labs of HP, and the Air Force Research Laboratory — demonstrate the potential of using large memristor crossbar arrays to perform analogue vector-matrix multiplication (Fig. 1). One of the main challenges here is to develop a stable multilevel memristor that offers good linearity and retention. Building on their previous understanding of hafnium oxide memristors with tantalum channels5, Xia and colleagues have successfully engineered memristor cells with good linearity, thus allowing constant readout conductance at varying voltage amplitudes. In addition, the device exhibited good retention characteristics for the available multistates. It is important to retain the written conductance in order to avoid deviations of the computing result from acceptable accuracy. The other challenge is to fabricate a memristor array with stable and reliable device performance while achieving a high array yield. By connecting a memristor to a transistor in series, the researchers implemented an architecture known as a 1T1R crossbar. In this configuration, the transistor reduces the sneak path current and allows both independent access and precise conductance tuning of each memristor in the array. With a well-developed integration process, the team fabricated a number of memristor arrays with different sizes up to 128 × 64. The 128 × 64 array achieved a high device yield of 99.8% and changeable analogue conductance.
Owing to the performance of their large memristor arrays, Xia and colleagues were able to experimentally demonstrate applications relevant to the development of IoT and edge computing. In particular, following an offline programming method, they tuned the conductance weight of the memristors to a pre-trained value and performed analogue vector-matrix multiplication in order to implement a discrete cosine transformation (DCT), a typical Fourier-related transform that is widely used for digital signal processing and image compression. A one-dimensional DCT test and a two-dimensional DCT image compression experiment both achieved the expected performance. Furthermore, parallel convolutional image filtering for a standard Lena image was demonstrated, thus illustrating the feasibility of using the memristor array for convolutional neural networks.
Memristor arrays, such as those developed by Xia and colleagues, offer an in-memory analogue computing approach that is attractive for edge computing applications used in the IoT (Fig. 1). Such hardware can process the analogue signals transmitted from different types of IoT sensors directly without any additional signal processing. Meanwhile, memristor systems with online learning abilities6,7 are able to provide highly connected hardware that is both low-power and smart. This online learning method tolerates intrinsic device errors and adapts to various cognitive tasks automatically. This analogue hardware may therefore improve the prospects of smart IoT, whereby the edge hardware is capable of realizing different kinds of tasks locally instead of sending data to the cloud, while also benefiting big-data analytics by performing deep-learning algorithms on edge equipment.
Significant further research is still required in order to deliver practical analogue computing based on memristors. For a start, the conductance of memristors must be decreased in order to reduce the current flow and hence the power consumption. The size of a memristor cell must also be scaled down to the nanoscale (it is currently around 4 μm × 4 μm), while retaining stable multistates and good linearity, in order to increase the packing density of the devices. To deliver a system capable of more intricate and practical applications, the required peripheral circuits will also need to be integrated on-chip with larger memristor arrays. Finally, it would be valuable if other computing algorithms that were adaptive to device defects and programming inaccuracy, such as online learning, could be implemented in such a large crossbar array.
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Wu, H., Yao, P., Gao, B. et al. Multiplication on the edge. Nat Electron 1, 8–9 (2018). https://doi.org/10.1038/s41928-017-0011-y
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