Skip to main content

Thank you for visiting nature.com. You are using a browser version with limited support for CSS. To obtain the best experience, we recommend you use a more up to date browser (or turn off compatibility mode in Internet Explorer). In the meantime, to ensure continued support, we are displaying the site without styles and JavaScript.

The future of electronics based on memristive systems

Abstract

A memristor is a resistive device with an inherent memory. The theoretical concept of a memristor was connected to physically measured devices in 2008 and since then there has been rapid progress in the development of such devices, leading to a series of recent demonstrations of memristor-based neuromorphic hardware systems. Here, we evaluate the state of the art in memristor-based electronics and explore where the future of the field lies. We highlight three areas of potential technological impact: on-chip memory and storage, biologically inspired computing and general-purpose in-memory computing. We analyse the challenges, and possible solutions, associated with scaling the systems up for practical applications, and consider the benefits of scaling the devices down in terms of geometry and also in terms of obtaining fundamental control of the atomic-level dynamics. Finally, we discuss the ways we believe biology will continue to provide guiding principles for device innovation and system optimization in the field.

This is a preview of subscription content, access via your institution

Relevant articles

Open Access articles citing this article.

Access options

Buy article

Get time limited or full article access on ReadCube.

$32.00

All prices are NET prices.

Fig. 1: The race towards future computing solutions.
Fig. 2: Hardware implementation of artificial neural networks in a memristor crossbar.
Fig. 3: Rapid advances in memristor technology.
Fig. 4: Possible evolution of the computing system.

References

  1. Chua, L. O. & Kang, S. M. Memristive devices and systems. Proc. IEEE 64, 209–223 (1976).

    Article  MathSciNet  Google Scholar 

  2. Strukov, D. B., Snider, G. S., Stewart, D. R. & Williams, R. S. The missing memristor found. Nature 453, 80–83 (2008).

    Article  Google Scholar 

  3. Lee, J. & Lu, W. D. On-demand reconfiguration of nanomaterials: when electronics meets ionics. Adv. Mater. https://doi.org/10.1002/adma.201702770 (2017).

  4. Wong, H.-S. P. et al. Metal–oxide RRAM. Proc. IEEE 100, 1951–1970 (2012).

    Article  Google Scholar 

  5. Waser, R., Dittmann, R., Staikov, G. & Szot, K. Redox‐based resistive switching memories — nanoionic mechanisms, prospects, and challenges. Adv. Mater. 21, 2632–2663 (2009).

    Article  Google Scholar 

  6. Govoreanu, B. et al. 10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation. In 2011 IEEE International Electron Devices Meeting (IEDM) 31.6.1–31.6.4 (2011).

  7. Yang, J. J., Strukov, D. B. & Stewart, D. Memristive devices for computing. Nat. Nanotech 8, 13–24 (2013).

    Article  Google Scholar 

  8. Torrezan, A. C., Strachan, J. P., Medeiros-Ribeiro, G. & Williams, R. S. Sub-nanosecond switching of a tantalum oxide memristor. Nanotechnology 22, 485203 (2011).

    Article  Google Scholar 

  9. Choi, B. J. et al. High-speed and low-energy nitride memristors. Adv. Funct. Mater. 26, 5290–5296 (2016).

    Article  Google Scholar 

  10. Kim, K.-H., Jo, S. H., Gaba, S. & Lu, W. D. Nanoscale resistive memory with intrinsic diode characteristics and long endurance. Appl. Phys. Lett. 96, 053106 (2010).

    Article  Google Scholar 

  11. Zhou, J. et al. Very low-programming-current RRAM with self-rectifying characteristics. IEEE Electron Device Lett 37, 404–407 (2016).

    Article  Google Scholar 

  12. Kim, S. et al. Experimental demonstration of a second-order memristor and its ability to biorealistically implement synaptic plasticity. Nano Lett. 15, 2203–2211 (2015).

    Article  Google Scholar 

  13. Jeong, Y., Kim, S. & Lu, W. Utilizing multiple state variables to improve the dynamic range of analog switching in a memristor. Appl. Phys. Lett. 107, 173105 (2015).

    Article  Google Scholar 

  14. Zidan, M. A. et al. Single-readout high-density memristor crossbar. Sci. Rep. 6, 18863 (2016).

    Article  Google Scholar 

  15. Yang, J. J. et al. Engineering nonlinearity into memristors for passive crossbar applications. Appl. Phys. Lett. 100, 113501 (2012).

    Article  Google Scholar 

  16. Zhou, J., Kim, K.-H. & Lu, W. D. Crossbar RRAM arrays: selector device requirements during read operation. IEEE Trans. Electron Devices 61, 1369–1376 (2014).

    Article  Google Scholar 

  17. Linn, E., Rosezin, R., Kügeler, C. & Waser, R. Complementary resistive switches for passive nanocrossbar memories. Nat. Mater. 9, 403–406 (2010).

    Article  Google Scholar 

  18. Hu, M. et al. Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) 1–6 (2016).

  19. Hilson, G. IMEC, Panasonic Push Progress on ReRAM. https://www.eetimes.com/document.asp?doc_id=1327307 (2015).

  20. Clarke, P. Crossbar ReRAM in Production at SMIC. https://www.eetimes.com/document.asp?doc_id=1331173 (2017).

  21. Shen, W. C. et al. High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process. In 2012 IEEE International Electron Devices Meeting (IEDM) 31.6.1–31.6.4 (2012).

  22. Fackenthal, R. et al. A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology. In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 338–339 (2014).

  23. Yu, S. & Chen, P.-Y. Emerging memory technologies: recent trends and prospects. IEEE Solid State Circuits Mag 8, 43–56 (2016).

    Article  Google Scholar 

  24. Silver, D. et al. Mastering the game of Go with deep neural networks and tree search. Nature 529, 484–489 (2016).

    Article  Google Scholar 

  25. Jo, S. H. et al. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett. 10, 1297–1301 (2010).

    Article  Google Scholar 

  26. Neftci, E. O., Pedroni, B. U., Joshi, S., Al-Shedivat, M. & Cauwenberghs, G. Stochastic synapses enable efficient brain-inspired learning machines. Front. Neurosci. 10, 241 (2016).

    Article  Google Scholar 

  27. Yu, S. et al. Scaling-up resistive synaptic arrays for neuro-inspired architecture: challenges and prospect. In 2015 IEEE International Electron Devices Meeting (IEDM) 17.3.1–17.3.4 (2015).

  28. Alibart, F., Zamanidoost, E. & Strukov, D. B. Pattern classification by memristive crossbar circuits using ex situ and in situ training. Nat. Commun. 4, 2072 (2013).

    Article  Google Scholar 

  29. Milo, V. et al. Demonstration of hybrid CMOS/RRAM neural networks with spike time/rate-dependent plasticity. In 2016 IEEE International Electron Devices Meeting (IEDM) 16.8.1–16.8.4 (2016).

  30. Prezioso, M. et al. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 521, 61–64 (2015).

    Article  Google Scholar 

  31. Sheridan, P. M. et al. Sparse coding with memristor networks. Nat. Nanotech. 12, 784–789 (2017).

    Article  Google Scholar 

  32. Choi, S., Shin, J. H., Lee, J., Sheridan, P. & Lu, W. D. Experimental demonstration of feature extraction and dimensionality reduction using memristor networks. Nano Lett. 17, 3113–3118 (2017).

    Article  Google Scholar 

  33. Burr, G. W. et al. Experimental demonstration and tolerancing of a large-scale neural network (165 000 synapses) using phase-change memory as the synaptic weight element. IEEE Trans. Electron Devices 62, 3498–3507 (2015).

    Article  Google Scholar 

  34. Linares-Barranco, B. & Serrano-Gotarredona, T. Memristance can explain spike-time dependent-plasticity in neural synapses. Preprint at http://precedings.nature.com/documents/3010/version/1 (2009).

  35. Gupta, I. et al. Real-time encoding and compression of neuronal spikes by metal-oxide memristors. Nat. Commun. 7, 12805 (2016).

    Article  Google Scholar 

  36. Ambrogio, S. et al. Unsupervised learning by spike timing dependent plasticity in phase change memory (PCM) synapses. Front. Neurosci. 10, 56 (2016).

    Article  Google Scholar 

  37. Chua, L. O. & Yang, L. Cellular neural networks: theory. IEEE Trans. Circuits Syst. I 35, 1257–1272 (1988).

    Article  MathSciNet  MATH  Google Scholar 

  38. Corinto, F., Ascoli, A., Kim, Y.-S. & Min, K.-S. in Memristor Networks (eds Adamatzky, A. & Chua, L.) 267–291 (Springer, New York, 2014).

  39. Chi, P. et al. PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In International Symposium on Computer Architecture (ISCA) 27–39 (2016).

  40. Sheri, A. M., Rafique, A., Pedrycz, W. & Jeon, M. Contrastive divergence for memristor-based restricted Boltzmann machine. Eng. Appl. Artif. Intell. 37, 336–342 (2015).

    Article  Google Scholar 

  41. Bojnordi, M. N. & Ipek, E. Memristive Boltzmann machine: a hardware accelerator for combinatorial optimization and deep learning. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) 1–13 (2016).

  42. Schuman, C. D. et al. A survey of neuromorphic computing and neural networks in hardware. Preprint at https://arxiv.org/abs/1705.06963 (2017).

  43. LeCun, Y., Bengio, Y. & Hinton, G. Deep learning. Nature 521, 436–444 (2015).

    Article  Google Scholar 

  44. Zidan, M. A. et al. Field-programmable crossbar array (FPCA) for reconfigurable computing. https://doi.org/10.1109/TMSCS.2017.2721160 (2017).

  45. Borghetti, J. et al. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature 464, 873–876 (2010).

    Article  Google Scholar 

  46. Yu, S. et al. Binary neural network with 16 Mb RRAM macro chip for classification and online training. In 2016 IEEE International Electron Devices Meeting (IEDM) 16.2.1–16.2.4 (2016).

  47. Kataeva, I., Merrikh-Bayat, F., Zamanidoost, E. & Strukov, D. Efficient training algorithms for neural networks based on memristive crossbar circuits. In International Joint Conference on Neural Networks (IJCNN) 1–8 (2015).

  48. Liu, C., Hu, M., Strachan, J. P. & Li, H. H. Rescuing memristor-based neuromorphic design with high defects. In 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) 1–6 (2017).

  49. Shafiee, A. et al. ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. In 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) 14–26 (2016).

  50. International technology roadmap for semiconductors (ITRS); http://www.itrs2.net/itrs-reports.html

  51. Borghetti, J. et al. A hybrid nanomemristor/transistor logic circuit capable of self-programming. Proc. Natl Acad. Sci. USA 106, 1699–1703 (2009).

    Article  Google Scholar 

  52. Kim, K.-H. et al. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. Nano Lett. 12, 389–395 (2012).

    Article  Google Scholar 

  53. Shulaker, M. M. et al. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature 547, 74–78 (2017).

    Article  Google Scholar 

  54. Chen, H.-Y. et al. HfOx based vertical RRAM for cost-effective 3D cross-point architecture without cell selector. In 2012 IEEE International Electron Devices Meeting (IEDM) 20.7.1–20.7.4 (2012).

  55. Kanerva, P. Hyperdimensional computing: an introduction to computing in distributed representation with high-dimensional random vectors. Cogn. Comput. 1, 139–159 (2009).

    Article  Google Scholar 

  56. Li, H. et al. Hyperdimensional computing with 3D VRRAM in-memory kernels: device-architecture co-design for energy-efficient, error-resilient language recognition. In 2016 IEEE International Electron Devices Meeting (IEDM) 16.1.1–16.1.4 (2016).

  57. Li, H., Wu, T. F., Mitra, S. & Wong, H.-S. P. Resistive RAM-centric computing: design and modeling methodology. IEEE Trans. Circuits Syst. I 64, 2263–2273 (2017).

    Article  Google Scholar 

  58. Terabe, K., Hasegawa, T., Nakayama, T. & Aono, M. Quantized conductance atomic switch. Nature 433, 47–50 (2005).

    Article  Google Scholar 

  59. Lee, J., Du, C., Sun, K., Kioupakis, E. & Lu, W. D. Tuning ionic transport in memristive devices by graphene with engineered nanopores. ACS Nano 10, 3571–3579 (2016).

    Article  Google Scholar 

  60. Liu, Q. et al. Controllable growth of nanoscale conductive filaments in solid-electrolyte-based ReRAM by using a metal nanocrystal covered bottom electrode. ACS Nano 4, 6162–6168 (2010).

    Article  Google Scholar 

  61. Hou, Y. et al. Sub-10 nm low current resistive switching behavior in hafnium oxide stack. Appl. Phys. Lett. 108, 123106 (2016).

    Article  Google Scholar 

  62. Alibart, F., Gao, L., Hoskins, B. D. & Strukov, D. B. High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm. Nanotechnology 23, 075201 (2012).

    Article  Google Scholar 

  63. Merced-Grafals, E. J., Dávila, N., Ge, N., Williams, R. S. & Strachan, J. P. Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications. Nanotechnology 27, 365202 (2016).

    Article  Google Scholar 

  64. Sheu, S.-S. et al. A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme. In 2009 Symposium on VLSI Circuits 82–83 (2009).

  65. O’Connor, P. & Welling, M. Deep spiking networks. Preprint at https://arxiv.org/abs/1602.08323 (2016).

  66. Shouval, H. Z., Bear, M. F. & Cooper, L. N. A unified model of NMDA receptor-dependent bidirectional synaptic plasticity. Proc. Natl Acad. Sci. USA 99, 10831–10836 (2002).

    Article  Google Scholar 

  67. Du, C., Ma, W., Chang, T., Sheridan, P. & Lu, W. D. Biorealistic implementation of synaptic functions with oxide memristors through internal ionic dynamics. Adv. Funct. Mater. 25, 4290–4299 (2015).

    Article  Google Scholar 

  68. Wang, Z. et al. Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing. Nat. Mater. 16, 101–108 (2017).

    Article  Google Scholar 

  69. Martin, S. J., Grimwood, P. D. & Morris, R. G. M. Synaptic plasticity and memory: an evaluation of the hypothesis. Annu. Rev. Neurosci. 23, 649–711 (2000).

    Article  Google Scholar 

  70. Valov, I. & Lu, W. D. Nanoscale electrochemistry using dielectric thin films as solid electrolytes. Nanoscale 8, 13828–13837 (2016).

    Article  Google Scholar 

  71. Fuller, E. J. et al. Li‐ion synaptic transistor for low power analog computing. Adv. Mater. 29, 1604310 (2017).

    Article  Google Scholar 

  72. Izhikevich, E. M. Simple model of spiking neurons. IEEE Trans. Neural Netw. Learn. Syst 14, 1569–1572 (2003).

    Article  Google Scholar 

  73. Funck, C. et al. Multidimensional simulation of threshold switching in NbO2 based on an electric field triggered thermal runaway model. Adv. Elect. Mater. 2, 1600169 (2016).

    Article  Google Scholar 

  74. Gibson, G. et al. An accurate locally active memristor model for S-type negative differential resistance in NbOx. Appl. Phys. Lett. 108, 023505 (2016).

    Article  Google Scholar 

  75. Pickett, M. D., Medeiros-Ribeiro, G. & Williams, R. S. A scalable neuristor built with Mott memristors. Nat. Mater. 12, 114–117 (2013).

    Article  Google Scholar 

  76. Gao, L., Chen, P. Y. & Yu, S. NbOx based oscillation neuron for neuromorphic computing. Appl. Phys. Lett. 111, 103503 (2017).

    Article  Google Scholar 

  77. Kumar, S., Strachan, J. P. & Williams, R. S. Chaotic dynamics in nanoscale NbO2 Mott memristors for analogue computing. Nature 548, 318–321 (2017).

    Article  Google Scholar 

  78. Maass, W. Noise as a resource for computation and learning in networks of spiking neurons. Proc. IEEE 102, 860–880 (2014).

    Article  Google Scholar 

Download references

Acknowledgements

We acknowledge inspiring discussions with R. S. Williams, G. Astfalk, X. Zhu, W. Ma, F. Cai and Y. Jeong. This work was supported in part by the National Science Foundation (NSF) through grant CCF-1617315, by the Defense Advanced Research Program Agency (DARPA) through award HR0011-17-2-0018, and by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via contract number 2017-17013000002.

Author information

Authors and Affiliations

Authors

Contributions

W.D.L conceived the project. All authors performed the project planning and comparative analysis. All authors carried out the discussions and the manuscript writing at all stages.

Corresponding authors

Correspondence to John Paul Strachan or Wei D. Lu.

Ethics declarations

Competing interests

The authors declare no competing financial interests.

Additional information

Publisher’s note: Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Zidan, M.A., Strachan, J.P. & Lu, W.D. The future of electronics based on memristive systems. Nat Electron 1, 22–29 (2018). https://doi.org/10.1038/s41928-017-0006-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1038/s41928-017-0006-8

This article is cited by

Search

Quick links

Nature Briefing

Sign up for the Nature Briefing newsletter — what matters in science, free to your inbox daily.

Get the most important science stories of the day, free in your inbox. Sign up for Nature Briefing