Abstract

Memristor crossbars offer reconfigurable non-volatile resistance states and could remove the speed and energy efficiency bottleneck in vector-matrix multiplication, a core computing task in signal and image processing. Using such systems to multiply an analogue-voltage-amplitude-vector by an analogue-conductance-matrix at a reasonably large scale has, however, proved challenging due to difficulties in device engineering and array integration. Here we show that reconfigurable memristor crossbars composed of hafnium oxide memristors on top of metal-oxide-semiconductor transistors are capable of analogue vector-matrix multiplication with array sizes of up to 128 × 64 cells. Our output precision (5–8 bits, depending on the array size) is the result of high device yield (99.8%) and the multilevel, stable states of the memristors, while the linear device current–voltage characteristics and low wire resistance between cells leads to high accuracy. With the large memristor crossbars, we demonstrate signal processing, image compression and convolutional filtering, which are expected to be important applications in the development of the Internet of Things (IoT) and edge computing.

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Acknowledgements

This work was supported in part by the Air Force Research Laboratory (AFRL; grant no. FA8750-15-2-0044), the US Air Force Office for Scientific Research (AFOSR; grant no. FA9550-12-1-0038), the Intelligence Advanced Research Projects Activity (IARPA; contract 2014-14080800008) and the National Science Foundation (NSF; ECCS-1253073). This work was performed in part at the Center for Hierarchical Manufacturing (CHM), an NSF sponsored Nanoscale Science and Engineering Center (NSEC) at University of Massachusetts, Amherst.

Author information

Affiliations

  1. Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, USA

    • Can Li
    • , Yunning Li
    • , Hao Jiang
    • , Wenhao Song
    • , Peng Lin
    • , Zhongrui Wang
    • , J. Joshua Yang
    •  & Qiangfei Xia
  2. Hewlett Packard Labs, Hewlett Packard Enterprise, Palo Alto, CA, USA

    • Miao Hu
    • , Eric Montgomery
    • , Jiaming Zhang
    • , Noraica Dávila
    • , Catherine E. Graves
    • , Zhiyong Li
    • , John Paul Strachan
    •  & R. Stanley Williams
  3. HP Labs, HP Inc., Palo Alto, CA, USA

    • Ning Ge
  4. Air Force Research Laboratory, Information Directorate, Rome, NY, USA

    • Mark Barnell
    •  & Qing Wu
  5. Department of Electrical and Computer Engineering, Binghamton University, Binghamton, NY, USA

    • Miao Hu

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Contributions

C.L., H.J., N.G., N.D., P.L. and Z.W. built the integrated chips. C.L., M.H., Y.L. and J.P.S. carried out the measurements. E.M., M.H. and J.P.S. built the measurement system. Y.L., M.H. and W.S. performed circuit simulation. J.Z. took the cross-sectional SEM and TEM images. J.P.S., J.J.Y. and Q.X. designed the experiments and supervised the project. Q.X., C.L., J.J.Y. and R.S.W. wrote the manuscript. All authors contributed to analysis of the results and commented on the manuscript.

Competing interests

The authors declare no competing financial interests.

Corresponding authors

Correspondence to John Paul Strachan or J. Joshua Yang or Qiangfei Xia.

Electronic supplementary material

  1. Supplementary Information

    Supplementary Figures 1–16, Supplementary Table 1, and Supplementary Notes 1–4.

Video

  1. Supplementary Video 1

    Programming of the conductance of memristors in a 64 × 64 array to arbitrary values within a pre-defined conductance range.

  2. Supplementary Video 2

    Real-time crossbar output with changing input frequencies.

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DOI

https://doi.org/10.1038/s41928-017-0002-z

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