Variability and Reliability of Graphene Field-Effect Transistors with CaF2 Insulators

Graphene is a promising material for applications as a channel in graphene field-effect transistors (GFETs) which may be used as a building block for optoelectronics, high-frequency devices and sensors. However, these devices require gate insulators which ideally should form atomically flat interfaces with graphene and at the same time contain small densities of traps to maintain high device stability. Previously used amorphous oxides, such as SiO2 and Al2O3, however, typically suffer from oxide dangling bonds at the interface, high surface roughness and numerous border oxide traps. In order to address these challenges, here we use for the first time 2nm thick epitaxial CaF2 as a gate insulator in GFETs. By analyzing device-to-device variability for over 200 devices fabricated in two batches, we find that tens of them show similar gate transfer characteristics. Our statistical analysis of the hysteresis up to 175C has revealed that while an ambient-sensitive counterclockwise hysteresis can be present in some devices, the dominant mechanism is thermally activated charge trapping by border defects in CaF2 which results in the conventional clockwise hysteresis. We demonstrate that both the hysteresis and bias-temperature instabilities in our GFETs with CaF2 are comparable to similar devices with SiO2 and Al2O3. In particular, we achieve a small hysteresis below 0.01 V for equivalent oxide thickness (EOT) of about 1 nm at the electric fields up to 15 MV/cm and sweep times in the kilosecond range. Thus, our results demonstrate that crystalline CaF2 is a promising insulator for highly-stable GFETs.

As a promising alternative to amorphous oxides and hBN, here we use for the first time 2 nm thick epitaxial calcium fluoride (fluorite, CaF 2 ) as a gate insulator in scalable GFETs with a graphene channel grown by chemical vapour deposition (CVD) and transferred onto the CaF 2 substrate.CaF 2 is an ionic crystalline insulator with good dielectric properties (E g = 12.1 eV, ε in range between 6.8 16 and 8.43 17 ) which forms quasi van der Waals interfaces with 2D materials 18 and at the same time can be epitaxially grown on Si(111) at 250 o C 19 in line with CMOS thermal budget requirements.This, in particular, makes CaF 2 an attractive candidate for the gate insulator of 2D FETs, even more so as CaF 2 allows the heteroepitaxy of 2D semiconductors on CaF 2 (111), as already confirmed for MoSe 2 20 and MoTe 2 . 21In our recent works 22,23 we have used CaF 2 to fabricate MoS 2 FETs with equivalent oxide thicknesses (EOT) down to 1 nm and with promising performance characteristics, such as a subthreshold swing (SS) down to 90 mV/dec, on/off current ratios up to 10 7 and high stability with respect to hysteresis and long-term drifts of the gate transfer characteristics.
Recently it has been also shown that CaF 2 can be epitaxially grown on silicene 24 which opens the path towards future top gate integration of 2D materials.
Thus, as the next step in this work we extend our previous findings towards More than Moore electronics based on 2D materials which suffers from similar problems of forming high quality interfaces with insulators with few charge traps. 10We open a way to the further development of scalable GFETs with various fluoride materials not limited to CaF 2 but including also MgF 2 or SrF 2 [25][26][27] and attempt to estimate the real potential of CaF 2 /graphene technologies by benchmarking the device-to-device variability, hysteresis and bias-temperature instabilities (BTI) of the gate transfer characteristics.We examine more than 200 GFETs with different channel dimensions and study the hysteresis and BTI dynamics in these devices for a broad range of temperatures from 25 o C to 175 o C.After minimizing the impact of non-insulator defects by annealing at 175 o C, we demonstrate that the stable clockwise hysteresis as well as the BTI drifts in our GFETs with CaF 2 are comparable to those in GFETs and MoS 2 FETs with SiO 2 and Al 2 O 3 , despite being subjected to higher gate bias stresses.It is worth noting that the use of thin insulators allows to achieve gate fields of up to 15 MV/cm which is higher than in most previously studied devices with 2D channels.
This constitutes the worst case scenario in terms of gate bias stress and thus makes the small observed degradation more valuable.Therefore, we conclude that CaF 2 is a promising insulator for next-generation graphene technologies, including Hall sensors for high temperature applications 28 which would benefit from stable behavior of our GFETs at least up to 175 o C. Furthermore, by using just 2 nm thick CaF 2 layers we for the first time achieve CMOS-compatible gate voltage operation ranges of only several Volts for our GFETs, while also reducing the power consumption and improving the sensitivity.
Although our first proof-of-concept GFETs with CaF  cm −3 ) and highly doped (N D = 5 × 10 18 cm −3 ) n-Si(111) substrates (Batch#1 and Batch#2, respectively) using an established molecular beam epitaxy method at a growth temperature of 250 o C, 19 similar to our previous works on CaF 2 /MoS 2 FETs. 22,23 avoid leakage currents from the large contact pads, they have been isolated with 10 nm Al 2 O 3 layers grown by plasma enhanced atomic layer deposition before sputtering 25 nm Pd source and drain contacts.Next, a commercial CVD-grown graphene film was transferred onto the substrate using a PMMA assisted transfer method and patterned with an oxygen plasma.More details about the CaF 2 growth and fabrication process of our GFETs can be found in the Methods section.
The schematic layout of our GFETs is shown in Fig. 1a.The obtained arrays contain hundreds of devices with channel dimensions (L ×W ) from 160 µm ×100 µm down to 9 µm ×3 µm, the optical images of the device structures with different dimensions are shown in Fig. 1b,c,d.In Fig. 1e we show that the gate leakage current is negligible as compared to the drain current while also being far below the density of 1 A/cm 2 at V G = 1 V, a guideline for scaled devices. 31As demonstrated in Fig. 1f, typical I D -V G characteristics of our devices with L × W = 80 µm ×50 µm exhibit relatively high currents up to 32 µA/µm within few Volts operation range due to the highly downscaled thickness of the gate insulator to only 2 nm.At the same time, the I D -V D characteristics presented in Fig. 1g show good current control with some kinks typical for ambipolar GFETs. 32Using a similar fabrication process but without isolating the contact pads, we also fabricated similar back-gated GFETs on highly doped Si substrates with 90 nm SiO 2 and 36 nm Al 2 O 3 and used them as a reference when comparing the obtained results.
We also note that since this is the first proof of concept study of GFETs with CaF 2 which employs transferred graphene films and non-protected channels, we did not focus on achieving the highest possible field-effect mobilities.2][13] However, it is expected that a more carefully adjusted device fabrication process could result in considerably improved mobilities owing to the quasi van der Waals nature of the CaF 2 /graphene interface.In particular, possible cracks of the already transferred graphene films due to the chemical inertness of CaF 2 (111) surfaces 18 have to be avoided when developing specific transfer methods for this type of substrates.Furthermore, long ambient exposure of the CaF 2 surface prior to fabrication of GFETs was unavoidable for these prototypes but should be minimized in the future.

Si Pd 25nm
Al O 10nm Gate current density < 1A/cm

Device-to-device variability
We start with a statistical analysis of the I D -V G characteristics measured for our GFETs with different sizes.As shown in Fig. 2a for our Batch#1 GFETs fabricated on moderately doped Si, already at this early stage of research over 30% of devices from the most representative group of GFETs with 80 µm ×50 µm dimensions exhibit very similar or even nearly identical I D -V G characteristics, even though in overall the device-to-device variability is still sizable (see Fig. S1 in the Supporting Information (SI)).In Fig. 2b we show the distribution of the Dirac current vs. Dirac voltage points (I Dirac vs. V Dirac ) for all 116 studied devices and note that the variability is stronger for GFETs with smaller channels.This is likely because our CVD-grown graphene is polycrystalline and thus larger devices may contain several complete grains within the channel, while the channel area of their smaller counterparts can be affected considerably by the grain boundaries.Since these grain boundaries significantly affect the electrostatics and carrier transport in the channel, broader distributions of I Dirac and V Dirac for smaller devices are to be expected.Furthermore, the same argumentation holds true for local imperfections and charges at the CaF 2 surface.In general, it is expected that there are microscopic inhomogeneities in the grown CaF 2 layers and impurities that have attached to the CaF 2 surface during transport and processing before the graphene layer transfer.These atomic defects will have a more pronounced impact on the charge transport for small area devices as compared to larger area ones. 33Another factor contributing to the variability could be different contact resistances of the pads due to some imperfections in their processing (see Fig. S2 in the SI).Thus, we expect that by further optimizing the CVD growth of the graphene channel and the device fabrication techniques, as well as the CaF 2 growth and the overall device fabrication flow, it may be possible to considerably reduce this variability.

Dirac Voltage [V]
116 devices V Dirac for all 116 devices; the number of devices with the corresponding channel dimension is marked in brackets in the legend.The measurements have been performed before any annealing step and some smaller devices have a more positive V Dirac (for those GFETs we used a V G sweep range from 0 to 4 V), implying the existence of a significant amount of negative charge at the interface.
In Fig. S3 in the SI we also show that GFETs from Batch#2 which we have fabricated later on highly doped Si substrates have very similar In addition, we have repeated the variability measurements on our Batch#1 GFETs following 6 months of storage under a moderate vacuum of about 600 torr.We found that at least 35 out of 116 GFETs remained functional and thus analyzed the device-to-device variability under the impact of elevated temperatures, while ignoring about 10 % of outliers with too positive V Dirac above 2 V (Fig. 2b) in our statistics.As shown in Fig. 3a for one representative GFET, at room temperature the measured I D -V G characteristic does not change significantly following long storage.However, annealing at 175 o C results in a negative shift of V Dirac which becomes more pronounced after a week at high temperature and does not recover after cooling back to 25 o C.This is likely caused by evaporation of some impurities from graphene or adsorbates which could serve as fixed charges and affect V Dirac .
The I Dirac vs. V Dirac distributions obtained for 35 devices with channel dimensions ranging from 40 µm ×20 µm down to 9 µm ×3 µm (Fig. 3b) suggest that this negative drift of V Dirac is a common feature for all GFETs on CaF 2 .Furthermore, the variability in V Dirac becomes smaller after annealing, as also confirmed by the statistical distributions shown in Fig. 3c.
Thus, we suggest that a thermal treatment of the devices at 175 o C should allow to exclude side effects related to the ambient impact on our GFETs, thus revealing the hysteresis dynamics which could be attributed solely to border insulator defects in CaF 2 .

Hysteresis dynamics and reliability
In Fig. 4 we analyze the hysteresis dynamics in GFETs with 80 µm ×50 µm channels.Among five selected devices, four are from Batch#1 which have not experienced any annealing and one is from Batch#2 which has been subjected only to initial annealing, i.e. 2 days at 100 o C followed by 5 hours at 175 o C. We can see that all devices have similar I D -V G characteristics which confirms the good reproducibility of our GFET technology.The hysteresis width (∆V H ) vs. reciprocal sweep time (1/t sw ) dependencies 34 measured for these GFETs are shown in Fig. 4b.While all devices from Batch#1 exhibit switching of the hysteresis from counterclockwise at faster sweeps to clockwise at slower sweeps, a typical GFET from Batch#2 has only a small clockwise hysteresis.In Fig. S5 in the SI we show the I D -V G characteristics of these devices measured using different sweep rates and observe that the clockwise hysteresis which appears for slow sweeps for Batch#1 GFETs is accompanied with a permanent negative drift of V Dirac .We suggest that while the conventional clockwise hysteresis is caused by fast insulator defects located close to the CaF 2 /graphene interface, the permanent drift accumulated during multiple sweeps is similar to bias-temperature instabilities (BTI) known from Si technologies, 35  The ∆V H vs. 1/t sw dependencies for the same GFETs.Compared to GFETs from Batch#1, the device from Batch#2 has only a small clockwise hysteresis at slow sweeps with no counterclockwise hysteresis at fast sweeps.
To understand the origins of the observed hysteresis dynamics and in particular the counterclockwise hysteresis, we have performed a similar analysis on GFETs with smaller channel areas before thermal annealing.In Fig. 5a,b we show the GFETs with 9µm ×3µm and 40µm ×20µm channel dimensions which exhibit similar hysteresis at different sweep rates.As confirmed in Fig. 5c for a larger statistics of seven GFETs, despite the overall variability in ∆V H (1/t sw ) curves, some devices with different sizes show The ∆V H vs. 1/t sw dependencies for seven GFETs with different channel dimensions.While there is some variability in the hysteresis dynamics, some devices with different sizes have identical hysteresis and thus this effect appears to be independent of the channel dimensions.
nearly identical hysteresis dynamics.Thus, this variability is not directly related to the channel dimensions but rather to the local density and type of defects near the channel.At the same time, it is remarkable that some of these smaller GFETs exhibit a counterclockwise hysteresis even at slow sweeps, while the others have purely clockwise hysteresis which becomes larger for slow sweeps and thus indicates a standard charge trapping mechanism at border traps in the CaF 2 close to the channel.To benchmark the origin of the counterclockwise hysteresis, we have also performed hysteresis measurements after 10 minutes of ambient exposure.As shown in Fig. S6 in the SI, in the device with initially dominant counterclockwise hysteresis this hysteresis becomes more pronounced following the ambient exposure, while the clockwise hysteresis in the second device slightly decreases without any switching to the counterclockwise direction.Therefore, we suggest that this counterclockwise hysteresis is mostly due to the interaction of our bare channel GFETs with the ambient environment while being unlikely related to defects in CaF 2 .The possible reasons for this behavior could include, for instance, interaction of defects in graphene with adsorbates or the diffusion of oxygen through imperfections in CaF 2 to the Si/CaF 2 interface.A counterclockwise hysteresis could for example be caused by charge trapping at defects close to the gate side, formed by the Si/CaF 2 interface. 37 this context, we next analyze the impact of high temperature annealing on the hysteresis in our GFETs directly after ambient exposure.In Fig. 6a A can be considerably suppressed (Fig. 6c), which makes the initially different ∆V H (1/t sw ) traces of two GFETs nearly identical after annealing (Fig. 6d).Furthermore, in Batch#2 GFETs (Fig. 6e,f) we do not see any counterclockwise hysteresis and observe only a conventional thermal activation of clockwise hysteresis which is consistent with our previous findings about charge trapping by border insulator defects situated near the interface with 2D channels. 34,38Remarkably, after about one week at 175 o C the hysteresis in these GFETs remains small and the dynamics observed at 25 o C do not change.This suggests that the density of border defects in CaF 2 is relatively low and that there is no thermally induced creation of new defects.Also, we note that the clockwise hysteresis in Batch#2 GFETs is smaller as compared to their Batch#1 counterparts, which could be explained by a more favorable work function 36 of the graphene films used during the second fabrication round.
Next we perform BTI measurements for the Batch#2 GFET studied in Fig. 6e,f  At the same time, no anomalous trends are present.This is in line with a small clockwise hysteresis measured for the same device which is actually a superposition of NBTI and PBTI accumulated during the sweeps 39 and again confirms low density of border traps in CaF 2 .
At the same time, the recovery of the observed degradation is rather weak in both cases, which suggests contributions from deep trap levels in CaF 2 .This is in line with our first principle calculations for possible defects in CaF 2 which could be Si interstitials (Si i ) or Si substituting Ca (Si Ca ) energetically aligned deep in the bandgap of CaF 2 . 37     holds with the elementary charge q, the density of active charge traps, N T , and the insulator capacitance C ins = ε 0 ε r /d ins .Hence, by introducing the equivalent oxide thickness with the SiO 2 dielectric constant of 3.9.As a consequence, the normalized hysteresis width is directly proportional to the density of active charge traps, N T , with physical constants as proportionality factors.Using this normalization, we compare in Fig. 8a

Conclusions
We fabricated over two hundred GFETs with CVD-grown graphene channels and 2 nm thick epitaxial CaF 2 insulators and performed an in-depth study of the device-to-device variability and hysteresis dynamics.Our results show that although grain boundaries of the channel or imperfections in CaF 2 layers may introduce some variability in the gate transfer characteristics, some nearly identical GFETs can be found already at this early stage of research.
We have also performed a comprehensive statistical analysis of hysteresis and BTI on many These results confirm that the use of crystalline CaF 2 as a gate insulator is a promising way to enable stable GFETs for sensors and optoelectronics, including Hall sensors for high temperature operations.Our findings can be generalized to include applications of various 2D materials and their devices for heterogeneous electronics coupling 2D and silicon CMOS elements. 43

Device fabrication
Fabrication of our GFETs consists of MBE growth of 2 nm thick CaF 2 films and photolithography to produce the device arrays with channel dimensions (L ×W ) from 160 µm ×100 µm down to 9 µm ×3 µm on the obtained Si/CaF 2 surfaces.
CaF 2 layers were grown on moderately doped (N D = 10 15 cm −3 ) and highly doped (N D = 5 × 10 18 cm −3 ) n-Si(111) substrates with a miscut angle of 5 to 10 minutes.Following careful chemical treatment of Si(111) surface, a protective oxide layer was formed using the method of Shiraki 44 and subsequently removed by annealing for 2 minutes at 1200 o C under ultra-high vacuum conditions (∼10 −8 −10 −7 Pa).After this, the CaF 2 film with 2 nm thickness was grown on the obtained atomically clean 7×7 Si(111) surface using an MBE process with the optimal growth temperature of 250 o C and deposition rate of about 1.3 nm/min.
A crystalline quality of the obtained CaF 2 layers was examined in situ using reflection highenergy electron diffraction (RHEED) 45 with an electron energy of 15 keV.The corresponding RHEED patterns which confirm high crystallinity with single-crystal structure of our thin CaF 2 films can be found in the Supporting Information of our previous work. 22r GFETs were fabricated on the obtained epitaxial Si/CaF 2 substrates using conventional photolithography.After defining the source and drain contact regions by photolithog-raphy, 10 nm Al 2 O 3 was deposited by plasma enhanced atomic layer deposition to isolate the contact pads and source and drain metals were deposited by sputtering 25 nm Pd, followed by a lift-off process.After fabricating the contacts, commercially available chemical vapor deposited graphene was transferred on the substrate by a PMMA assisted method.
Finally, the graphene was patterned by oxygen plasma to form the transistor channel which is bottom-contacted by Pd metal.
Using a similar approach, we have also fabricated back-gated GFETs with 90 nm SiO 2 and 36 nm Al 2 O 3 insulators to be used for reference in hysteresis comparison.However, considering larger insulator thickness, no isolation of contact pads was needed in that case.

Measurement technique
Electrical characterization of our GFETs with CaF 2 consisted in the measurements of the I D − V G characteristics and hysteresis dynamics.These measurements were performed

Figure 1 :
Figure 1: (a) Schematic structure of our back-gated GFETs with 2 nm CaF 2 insulators.Optical images of GFETs with L ×W of 160 µm ×100 µm (b), 80 µm ×50 µm (c) and smaller dimensions from 40 µm ×20 µm to 9 µm ×3 µm (d).(e) The gate leakage current through our thin CaF 2 layers is small compared to the drain current through the GFET channel with a density far below 1 A/cm 2 at V G = 1 V. (f) Typical I D -V G characteristics of our GFETs measured at different drain voltages.(g) The I D -V D characteristics measured for the same GFET at different gate voltages exhibit ambipolar kinks.All provided results have been obtained for Batch#1 GFETs.

Figure 2 :
Figure 2: (a) I D -V G characteristics of 11 similar GFETs with 80µm ×50µm channels selected from our total statistics of 116 Batch#1 devices with different channel dimensions.(b) Distribution of I Dirac vs.V Dirac for all 116 devices; the number of devices with the corresponding channel dimension is marked in brackets in the legend.The measurements have been performed before any annealing step and some smaller devices have a more positive V Dirac (for those GFETs we used a V G sweep range from 0 to 4 V), implying the existence of a significant amount of negative charge at the interface.

Figure 3 :
Figure 3: (a) Transformation of the I D -V G characteristics following 6 months of storage under a moderate vacuum, subsequent annealing at 175 o C and cooling back to 25 o C. (b) Distribution of I Dirac vs. V Dirac for 35 devices at 25 o C, in the beginning and in the end of 175 o C annealing in vacuum (10 −6 torr), and at 25 o C after annealing.(c) Statistical distributions of V Dirac values for these devices at the same temperature/annealing conditions and at V D = 0.3 V.

Figure 4 :
Figure4: (a) Double sweep I D -V G characteristics of five GFETs with 80µm ×50µm channels measured using ultra-slow sweeps with S = 0.002 V/s.Among these devices, there is one GFET from Batch#2.(b) The ∆V H vs. 1/t sw dependencies for the same GFETs.Compared to GFETs from Batch#1, the device from Batch#2 has only a small clockwise hysteresis at slow sweeps with no counterclockwise hysteresis at fast sweeps.

Figure 5 :
Figure 5: Double sweep I D -V G characteristics of GFETs with 9µm ×3µm (a) and 40µm ×20µm (b) channels measured with different sweep rates.The hysteresis dynamics observed for these two devices are very similar.(c)The ∆V H vs. 1/t sw dependencies for seven GFETs with different channel dimensions.While there is some variability in the hysteresis dynamics, some devices with different sizes have identical hysteresis and thus this effect appears to be independent of the channel dimensions.

Figure 6 :
Figure 6: Double sweep I D -V G characteristics measured for our Batch#1 GFETs at T = 25 o C, 175 o C and 25 o C after annealing using S = 0.002 V/s.Just after 10 minutes of ambient exposure, Device A (a) exhibited counterclockwise and Device B (b) clockwise hysteresis.(c) At 100 o C and at 175 o C the counterclockwise hysteresis in Device A is strongly suppressed, and after annealing at 175 o C both devices exhibit similar clockwise hysteresis (d).(e,f) The corresponding results for a Batch#2 GFET which show no counterclockwise contribution and conventional thermal activation of charge trapping.These GFETs experienced an initial annealing of 2 days at 100 o C and 5 hours at 175 o C prior to the first measurement round.
,b we show the I D -V G characteristics of two GFETs with counterclockwise (Device A) and clockwise (Device B) hysteresis at different temperatures up to 175 o C and back at 25 o C after six days annealing required to complete our measurements at 175 o C. Indeed, the counterclockwise hysteresis in Device

Figure 7 :
Figure 7: (a) Evolution of the I D -V G under NBTI stress measured for our Batch#2 GFET with L × W = 80 µm ×50 µm (left) and the corresponding recovery traces for increasing stress biases, V G,stress (right).(b) The corresponding results for PBTI measured on the same device.

Figure 8 :
Figure 8: (a) Comparison of the normalized hysteresis widths in different back-gated 2D FETs (1-34 2-40 3-22 ) and Si FETs for the sweep time of about 2 ks versus the effective gate field (V G,max −V G,min )/d ins (left) and versus EOT (right).For comparing the hysteresis widths on technologies with different gate stacks, the hysteresis widths were normalized by EOT.The measured clockwise hysteresis in our GFETs with CaF 2 is comparable to the normalized hysteresis widths reported in 2D devices, with the hysteresis on our Batch#2 CaF 2 GFETs being the smallest and meeting the target values.(b) Comparison of normalized PBTI (top) and NBTI (bottom) drifts measured with a small time delay of about 0.5 s after stress and after 10 hours of recovery versus the insulator field V G,stress /d ins (left) and versus EOT (right).Measured Dirac shifts were normalized by EOT, revealing a comparable BTI on our GFETs with CaF 2 as in devices with SiO 2 and Al 2 O 3 gate insulators, despite being stressed at much higher gate fields.
GFETs at temperatures of up to 175 o C. Our findings suggest that the initially observed, ambient-sensitive, counterclockwise hysteresis can be fully suppressed by 175 o C annealing in our first batch of GFETs and is not present in the devices from the second batch.The remaining clockwise hysteresis can be attributed to border traps in CaF 2 and is on devices from the second batch smaller than in reference GFETs with SiO 2 and Al 2 O 3 .The main milestone of our study is that we have achieved a hysteresis below 0.01 V for an equivalent oxide thickness (EOT) of about 1 nm at electric fields up to 15 MV/cm and long sweep times in the kilosecond range, reaching the target values set by commercial silicon technologies.
using a Keithley 2636 parameter analyzer in the chamber of a Lakeshore probestation in a vacuum (∼5×10 −6 torr), in complete darkness and at temperatures ranging from 25 o C to 175 o C, with the days-long measurements at 175 o C being also considered as an annealing step.The hysteresis of the I D − V G characteristics was studied using our established measurement technique 34 based on double sweeps with varied sweep times.The hysteresis width was obtained as a difference of V Dirac between forward and reverse sweep I D − V G characteristics.We express our results by plotting the hysteresis widths ∆V H versus the reciprocal sweep time 1/t sw .For comparing hysteresis widths and Dirac point shifts for different devices and measurement conditions, we extract ∆V H for a sweep time in the kilosecond range, normalize it by EOT and plot it versus the effective gate field (V G,max − V G,min )/d ins , where (V G,max − V G,min ) is the width of the sweep range and d ins is the insulator thickness, and also versus EOT. 15 41e post-annealing hysteresis observed for our CaF 2 GFETs, for back-gated MoS 2 FETs with SiO 2 34,40 and CaF 2 , 22 for commercial silicon FETs and also for our reference back-gated GFETs with SiO 2 and Al 2 O 3 (see more details in Fig.S7 in the SI).∆VH /EOT measured at t sw = 2 ks is plotted versus the effective gate insulator field (V G,max − V G,min )/d ins , where V G,max andV G,min are the boundaries of the gate sweep range, and also versus EOT.Indeed, owing to the crystalline CaF 2 and the highly scaled insulator thickness, the observed hysteresis is small and comparable to the normalized hysteresis observed in other devices, even at high effective gate insulator fields.This comparison shows that the density of activated charge traps N T in our Batch#2 GFETs is minimal, leading to the best observed performance.Moreover, for the Batch#2 GFETs the targets of ∆V H < 0.01 V for EOT < 1 nm and a gate field of E ins > 10 MV/cm are reached, showing a smaller hysteresis than measurements on a commercial Si/high-k technology.For reference we show a similar comparison in Fig.S8in the SI without any normalization, directly comparing the measured ∆V H , demonstrating how a scaled EOT is very important to achieve small absolute numbers for the hysteresis width, ∆V H and further illustrating the excellent performance of our GFETs.Additionally, in Fig.8bwe compare the NBTI and PBTI shifts of the Dirac voltage normalized by EOT as a function of the stress insulator field and EOT for our GFETs with CaF 2 , Al 2 O 3 and SiO 2 to the BTI on a commercial silicon high-k scaled logic node.41For the three GFET batches, the absolute stress voltages were 3, 10 and 30 V, respectively.In agreement with the hysteresis results for GFETs with CaF 2 , the normalized BTI shifts are comparable for all three gate insulators, even though CaF 2 has experienced considerably higher electric fields.In the CaF 2 GFETs the electric gate fields and EOT targets are achieved, even though the BTI target of 0.03 V according to the International Roadmap of Semiconductor Devices and Systems 42 is out of reach for any of the compared GFET technologies.Again, in Fig.S8 in the SI a comparison of the directly measured ∆V Dirac values is shown, confirming the small BTI seen in our CaF 2 gated GFETs.These results demonstrate that CaF 2 is a promising insulator which allows to fabricate ultra-scaled 2D devices of high stability with respect to charge trapping.