Introduction

The recent trend in the development of electronic devices is directed toward miniaturization, portability, and high performance, well agreed with the prediction of Moore’s Law. However, the imminent end of Moore’s Law has already been expected over the last few years. To continue to keep up with the miniaturization requirements, shortening the device channel is a traditional solution, although the challenge with this approach is the rise of leakage current due to short-channel effects. For this reason, modified device structures, such as the fin field-effect transistors (FinFETs), were introduced. In FinFET, the transistor channel is constructed into a fin-like shape forming a wrap-around gate structure. This three-dimensional (3D) design enables control over the on/off states of FinFETs from both sides of the circuit, thereby offering better control due to more effective leakage current suppression. Aside from improving the device design, many efforts have also been made to explore new materials that can replace silicon for shorter FET channel implementations. Atomically thin two-dimensional (2D) layered materials like semiconducting transition metal dichalcogenides (TMDs) represent the ultimate limit of miniaturization in the vertical direction, holding great potential for advanced nanoelectronics1,2. Attention has been paid mainly to molybdenum disulfide (MoS2), owing to its large bandgap (~1.9 eV), high carrier mobility, significant on/off current ratio, and relatively small subthreshold swing3,4,5,6,7. However, MoS2 exhibits only n-type behavior in most previous studies, hampering its use in complementary metal-oxide-semiconductors (CMOS). To solve this, one feasible strategy is to integrate MoS2 with other p-type transistors. For instance, a 2D CMOS inverter was constructed by integrating an n-type MoS2 FET and a p-type WSe2 FET into a planar heterostructure8. A flexible CMOS inverter was designed by fabricating a p-type Si nanomembrane FET and an n-type MoS2 FET on the same organic substrate9. Recently, we also realized a polarity-controllable MoS2 transistor in a single device for logic inverter application10.

In addition to the above efforts and achievements, advanced integration techniques, particularly 3D integration schemes, have also been presented to ensure the more rapid growth of transistors per chip. 3D integrated circuits (3D ICs)11,12 consist of vertically stacked and interconnected active chips, carrying components like transistors and sensors. 3D ICs promise a smaller form factor, higher integration density, lower power consumption, better signal integrity, and heterogeneous integration compared to conventional 2D ICs. Utilizing both a 2D TMD channel and the finFET design into 3D ICs can combine their respective advantages11,13,14; however, the intuitive question is whether 2D materials-based devices and their fabrication are compatible with existing Si-based semiconductor technology. This question has yet to be examined, although 2D materials and related devices have been broadly studied in academia. In general, stacking schemes in 3D ICs include wafer-to-wafer, die-to-wafer, and die-to-die using aligning, thinning, bonding, and through-silicon-via (TSV) technique for constructing 3D interconnected circuits15,16,17,18. However, these manufacturing methods tend to be accompanied by some concerns, including sizeable parasitic capacitance and enormous residual thermal/mechanical stress in chip substrates. Therefore, incorporating 2D materials into 3D ICs is considered difficult by using conventional TSV-based 3D integration. Auspiciously, monolithic 3D ICs (M3D ICs), enabled by sequential integration of device tiers on the same wafer by deposition or recrystallization, is a relatively feasible strategy for incorporating 2D materials in 3D ICs11,13,17. The high process temperature used during the sequential processes should, nevertheless, be prevented to reduce the thermal budget and to avoid affecting the performance of the lower layer active devices.

This work demonstrates a prototype monolithic 3D CMOS inverter with a vertical-stacking configuration of an upper-tier n-channel MoS2 transistor and a lower-tier p-channel Si FinFET with 20 nm fin width. We utilize the contact hole etching (CHE) technique to fabricate monolithic intertier vias (MIVs) to interconnect the top and bottom transistors, employ chemical mechanical planarization (CMP) to thin down the passivation layer, and perform wet-transfer method towards building the MoS2 FET on the upper-tier. While the lower-tier Si FinFET exhibits very minimal gate leakage current as expected, the upper-tier MoS2 FET also demonstrated negligible leakage. The whole process is kept at a low temperature to comply with the thermal budget needed to avoid the degradation of the lower-tier devices during subsequent fabrication of the upper-tier components. Symmetrical characteristic curves have been observed between the MoS2 FET and the Si FinFET after changing the MoS2 FET’s control structure from back-gated to top-gated, which is an important consideration prior to integrating the devices into a CMOS structure. Consequently, as made apparent by a smoother interface between the e-beam vapor deposition (e-beam VD) grown Al2O3 top-gate and the MoS2 flake, the MoS2 FET’s performance was proven unaffected by the low-temperature dielectric deposition process. The fabricated Si FinFETs display an averaged on/off current ratio of 106 and an on-current of 10−5 A, while MoS2 FETs show an on/off current ratio of 106 and an on-current near 10−6 A—implying further a consistent performance between the two unique structured devices as needed for CMOS implementation. The Si FinFET on the bottom tier maintains good electrical properties after subsequent MoS2 FET fabrication, proving that our low-temperature monolithic-like integration method can indeed allow successful integration of 2D materials-based devices with Si-based devices. The resulting CMOS inverter exhibits inversion signals with a maximum gain value of ~38. It is worth noting that the integration was enabled by deliberately adopting industrially matured techniques, such as CMP and e-beam evaporation, to ensure its compatibility to the existing 3D IC process and to the semiconductor industry in general. Hence, this work demonstrates a feasible manufacturing process to integrate 2D materials into 3D ICs for back-end circuit applications.

Results and discussion

Manufacturing of M3D CMOS inverter

Figure 1a–g illustrates the step-by-step process of fabricating the proposed monolithic 3D CMOS inverter, in which a top-gated MoS2 FET was built on top of a Si FinFET. First, a fin-shaped Si channel was fabricated on a SiO2 substrate before a HfO2 dielectric, wrapped around the channel, was deposited. A TaN/TiN electrode was then placed on the dielectric sheet to complete the p-type Si FinFET on SiO2 substrate (Fig. 1a). A passivation/supporting layer that separates the lower-tier Si FinFET from the upper-tier is needed to avoid leakage current or coupling effects between the vertically adjacent devices. Hence, a 750 nm tetraethyl orthosilicate (TEOS) layer was deposited on Si FinFET to serve as the precursor for synthesizing SiO2 via a plasma-enhanced chemical vapor deposition (PECVD) process19. The intermediate SiO2 layer was then thinned down to 250 nm using CMP (Fig. 1b). Vertical holes were then made through the SiO2 layer via the CHE method and then filled with the Al/Cu metals by e-beam evaporation method to connect the Si FinFET to the upper surface of the SiO2 layer (Fig. 1c).

Fig. 1: Schematic and process flow of the 3D Si-MoS2 CMOS inverter.
figure 1

a Completed Si FinFET on SiO2/Si substrate. b Deposition of SiO2 via PECVD to create an intermediate layer on the FinFET for passivation, followed by chemical mechanical polishing for the thinning and flattening of the SiO2 layer. c Building the monolithic intertier vias (MIVs) by employing contact hole etching and e-beam vapor deposition. d Transferring the monolayer MoS2 triangles on the SiO2 layer. e Fabrication of source/drain electrodes connected to MoS2 using e-beam lithography and e-beam vapor deposition. f E-beam vapor deposition of Al2O3 dielectric as the top-gate on MoS2. g Schematic of a CMOS inverter fabricated by vertically integrating a p-channel Si FinFET and an n-channel monolayer MoS2 transistor. The inset shows the cross-sectional structure of the Si FinFET. h SEM image of the Si FinFET. Scale bar: 100 μm. i TEM image showing the cross-section of Si FinFET. Scale bar: 25 nm. j Optical image showing the top view of the fabricated 3D CMOS inverter. Scale bar: 100 μm. k Zoom-in image showing the MoS2 FET in k. Scale bar: 10 μm.

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It should be mentioned that the CMP treatment for surface planarization and the CHE method have been commonly used in 3D ICs and adopted here to evaluate process compatibility. Meanwhile, to build the n-type MoS2 FET on the surface of intermediate SiO2 layer, monolayer MoS2 triangles were synthesized on a c-plane sapphire or SiO2/Si substrate using CVD and transferred onto the SiO2 surface by wet-transfer technique (Fig. 1d). The size of MoS2 crystals selected for FET fabrication was 10–20 μm. To anchor MoS2 samples on the SiO2 intermediate layer, we placed the substrate on a hot plate with a tilt angle of about 60°, and then baked the chip at 110 °C for 30 min under ambient conditions. The detailed procedure of wet-transfer has been thoroughly depicted in our previous study20. Ti (10 nm)/Ni (50 nm) source/drain electrodes were subsequently deposited onto the MoS2 sheet (Fig. 1e). To form the high-k/metal gate, a 20 nm Al2O3 dielectric layer was placed on the MoS2 flake using e-beam VD between the source and drain electrodes (Fig. 1f), followed by a Ti (10 nm)/Ni (50 nm) top-gate electrode to form the MoS2 FET. Finally, another Ti (10 nm)/Ni (50 nm) electrodes were made to connect the upper-tier MoS2 FET and the lower-tier Si FinFET (Fig. 1g) to complete the monolithic 3D CMOS inverter. It is noteworthy that, from PECVD SiO2 process to MoS2 FET fabrication, the fabrication processes were conducted at the temperature lower than 200 °C, which complied with the low thermal budget required by BEOL processes21. Figure 1h–k show the photographs and TEM images of the fabricated 3D CMOS inverter comprising a p-Si FinFET and an n-MoS2 FET. More details about the fabrication processes are available in the Experimental section.

Characterizations of Si FinFETs and back-gated MoS2 FETs

The electrical properties and structures of individual FETs were first evaluated before the integration stage. Figure 2a shows the transfer characteristic curves (drain current vs. gate voltage, IDS–VGS) of the 12 isolated Si FinFETs with 20 nm fin width on the same wafer. The IDS of the Si FinFETs were measured between the source and drain electrodes of the respective devices by sweeping the gate voltage (VGS) from –2.0 V to 1.0 V at a drain voltage VDS = −1 V. Negative VGS enhances the IDS, confirming that the transistor channels are p-type. The IDS–VGS graph also displays that the on/off current states changed at around VGS = 0 V, which corresponds to the threshold voltage (Vth) of the transistors. Specifically, the Vth value is obtained from the linear region of the transfer curve based on the linear extrapolation method, as shown in the inset of Fig. 2a. The output characteristic (IDS–VDS) curves of the representative Si FinFET (Fig. 2b) displays that the IDS is near zero and the channel is off when VGS is higher than 0.1 V, reaffirming its p-type role in the CMOS circuit. The IDS reaches up to about 35 μA at VGS = −2.0 V.

Fig. 2: Electrical characteristics of the Si FinFET.
figure 2

a Measured transfer characteristics of the 12 Si FinFETs spread on the same wafer (VDS = −1 V). The inset shows a linear fitting line to the transfer characteristic to estimate the threshold voltage (Vth). b Measured output characteristic of a FinFET at applied VGS = 0.1 V to −2 V.

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Spectroscopic and electrical properties of the MoS2 films were first characterized before they get employed for monolithic integration with Si-FETs. The optical properties of the MoS2 flakes used in the MoS2 FET fabrication were recorded before and after the wet-transfer process. The PL spectrum (Fig. 3a) of a representative MoS2 flake under 532 nm laser excitation shows an A exciton peak at 672 nm, indicating a semiconductor bandgap Eg ~1.85 eV9,22,23. Its Raman spectrum (Fig. 3b), under the same light condition, shows a difference (Δ) between the A1g and \({{{\mathrm{E}}}}_{2{{{\mathrm{g}}}}}^1\) peaks of about 17.8 cm−1, agreeing well with the feature of monolayer MoS2 reported in most studies22,23,24. In addition, the shift of the \({{{\mathrm{E}}}}_{2{{{\mathrm{g}}}}}^1\) vibration mode is an indication of defect concentration in 2D TMD materials25,26. There was no noticeable change in the \({{{\mathrm{E}}}}_{2{{{\mathrm{g}}}}}^1\) peak position found after wet-transfer, revealing that the quality of MoS2 was not seriously affected by the wet-transfer process. The PL/Raman mapping (Fig. 3c) with respect to the A exciton/Raman peak intensity shows consistency all throughout the sample. Based on these spectroscopic analyses, the CVD-grown MoS2 samples were identified to be monolayers with high uniformity.

Fig. 3: Material characterization and electrical performance of back-gated MoS2 FET on SiO2/Si.
figure 3

a Photoluminescence (PL) spectrum of MoS2. The inset shows a representative CVD-grown MoS2 flake used in this work. Scale bar, 5 μm. b Raman spectra showing A1g and \({{{\mathrm{E}}}}_{2{{{\mathrm{g}}}}}^1\) characteristic peaks of MoS2 before and after wet-transfer. c PL mapping for A exciton peak intensity at 1.85 eV and Raman mapping for the A1g and \({{{\mathrm{E}}}}_{2{{{\mathrm{g}}}}}^1\) peaks, all of which are obtained from the MoS2 triangle shown in the inset of a. d Measured transfer characteristics of 23 back-gate MoS2 FETs fabricated in different process batches (VDS = 1 V). Scale bar, 5 μm. e Measured output characteristics of a back-gated MoS2 FET at VGS = −15 V to 25 V in 5 V steps.

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Initially, back-gated MoS2 FETs on SiO2 layer were built and the electrical characteristic curves (Fig. 3d), performed using the same measuring parameters as those used in the Si FinFET, displayed consistent and steady n-FET performances among different devices, where the N-Methyl-2-Pyrrolidone (NMP) wet cleaning process played a critical role as discussed in our previous work27. The on-current level of these 23 back-gated MoS2 FETs was able to be tuned from 10−7 to 10−5 A depending on the channel length (from 3 to 0.16 μm), which served as a tuning nobe for optimizing the on-current and the on/off ratio to match with the Si FinFET. In addition, Fig. 3e displays the IDS–VDS characteristic curves of a representative device at different gate voltages showing that the IDS becomes zero when VGS is lower than −15 V, confirming its function as an n-type device for the CMOS circuit. The maximum IDS reached around 40 μA at VGS = 5 V. Evidently, however, the Vth of the back-gated MoS2 FETs are too far from the Si FinFET’s, consequently indicating an asymmetric relationship with the Si FinFET for CMOS application.

Performance of top-gated MoS2 FET on upper-tier

The prominent performance of top-gated FET structures compared to their back-gated counterparts28,29,30, and the known advantages of Al2O3 dielectrics, such as high dielectric constant, excellent stability, and a reported induced positive Vth shifting when used as a substrate replacing SiO231, have motivated the fabrication of top-gated Al2O3/MoS2 FET structures10,32 as the upper-tier device for this work. Apparently, the Vth of the developed top-gated MoS2 FETs, in which the result of a representative device is shown in Fig. 4a, has gotten closer and more symmetrical with that of the corresponding Si FinFET (Fig. 4b). The shifting of the Vth to a lower negative (near zero) value may arise from several possible factors, which include reduced fixed charges in the Al2O3 and a lower trap density at the MoS2/Al2O3 interface as governed by the numerical simulation in the previous report33. Concurrently, a more systematic investigation of this positive shifting of the Vth is in progress. The gate leakage current (IGS) in the top-gated device is also very minimal, which is the same order (~10−12 A) as in the back-gated operation. The smooth interface between the Al2O3 and MoS2 layers, as shown in the TEM image in Fig. 4c, implies that the Al2O3 deposition by e-beam has not caused pronounced damage to the MoS2 flake, in contrast to the atomic layer deposition (ALD) technique that could degrade the device performance. Looking closer to the characteristic curve of the top-gated MoS2 FET in Fig. 4a, the IDS has reached ~10–6 A and the Vth = −1.3 V. The on/off current ratios are approximately 104 and 105 at VDS = 0.05 V and 1.00 V, respectively. The subthreshold swing (SS) of the device can be obtained according to its definition, \(SS = \partial V_{{{{\mathrm{GS}}}}}{{{\mathrm{/}}}}\partial \log _{{{{\mathrm{10}}}}}I_{{{{\mathrm{DS}}}}}\), and has a value of 129.5 mV/dec at VDS = 1 V, which becomes smaller compared with the back-gated MoS2 FETs. Lastly, the field-effect electron mobility (μ) was calculated based on \(\mu = {\textstyle{L \over {W \cdot C \cdot V_{{{{\mathrm{DS}}}}}}}}\left( {{\textstyle{{\partial I_{{{{\mathrm{DS}}}}}} \over {\partial V_{{{{\mathrm{GS}}}}}}}}} \right)\), where L stands for the channel length, W the channel width, C the capacitance of the top-gate (Al2O3), and \(\partial I_{{{{\mathrm{DS}}}}}{{{\mathrm{/}}}}\partial V_{{{{\mathrm{GS}}}}}\) the slope of the transfer curve. The calculated μ value is 0.2 cm2 V−1 s−1.

Fig. 4: Electrical characteristics of top-gated MoS2 FET on upper-tier and lower-tier Si FinFET.
figure 4

Measured transfer characteristics of a a top-gate MoS2 FET on intermediate SiO2 layer and b a Si FinFET on Si/SiO2 (VDS = 0.05 V and 1.00 V). For the Si FinFET, the measurement was conducted before and after the MoS2 FET fabrication. In a and b, the gate current (IGS) was measured to acquire the level of the leakage current in the fabricated transistors. c Schematic of the top-gated MoS2 FET. The TEM image shows the cross-section of the top-gated MoS2 FET. Scale bar, 10 nm.

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The transfer characteristic of the Si FinFET with fin width of 20 nm was again measured in order to ensure good and unaffected electrical performance after the MoS2 FET fabrication. As shown in Fig. 4b, the measured transfer curves of the the Si FinFET at drain voltages VDS = 0.05 V and 1.00 V were found almost the same before and after the MoS2 FET fabrication, indicating that the subsequent MoS2 FET process had not damaged the electrical characteristic of the Si FinFET. This may strongly be attributed to the low-temperature processes used in building the upper-tier components. The SS of the Si FinFET can be estimated to 80.6 mV/dec at VDS = 1 V. The on-current value is increased to approximately 10–5 A at its maximum, and a negligible level of IGS with four orders of magnitude lower than the IDS is observed. For comparison purposes, the on/off current ratio of the Si FinFET and the MoS2 FET has the same order of magnitude, whereas the on-current of the former is an order of magnitude larger than that of the latter. The acceptable similarities of the electric current properties of the two unique structured devices imply a compatible performance between them, which is needed for CMOS implementation. Such matched electrical results have also been reliably obtained in other fabricated devices. Table 1 summarizes the measured parameters and electrical characteristics of the Si FinFET and the MoS2 FET that we deliberately used for the demonstration of our CMOS inverters. The size of the MoS2 FET is more significant than that of the Si FinFET by one order of magnitude. Likewise, the mobility of the former is one order of magnitude lower than that of the latter. Both FETs have almost similar SS values. The dimension of the MoS2 FET can be scaled to match with Si FinFET with the further improvement of the contact resistance and field-effect mobility. For this, utilizing Bi/Au as the contact metal is a promising strategy recently reported realizing a high on-current level for ultrashort channel 2D FETs2. The relevant experiments are needed to further improve our 3D CMOS device architectures.

Table 1 Transistor parameters of the p-type Si FinFET and n-type MoS2 FET combined in CMOS inverter.
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Demonstration of M3D CMOS inverter and benchmarks

After being verified with good electrical performance, the p-type Si FinFET and the n-type top-gated MoS2 FET were interconnected to form a 3D CMOS inverter. Figure 5a shows the inverter’s voltage transfer characteristics (VOUT vs. VIN) by varying the power supply voltage VDD from 0.1 V to 2.1 V in 0.5 V steps. An evident signal inversion was observed with high VOUT at low VIN, and vice versa, and the corresponding gain (∂VOUT/∂VIN) was successively obtained. The maximum gain in this CMOS is approximately 30.8 at VDD = 2.1 V. This inverter displays 5 μW power consumption in the static states. For the evaluation of its noise margin, Fig. 5b shows the forward and reverse curves of the inverter’s logic voltage level, where the logic low output voltage (Vol = 0.063 V), logic low input voltage (Vil = 1.006 V), logic high input voltage (Vih = 1.261 V), and logic high output voltage (Voh = 2.037 V) are shown. When the inverter is applied with a low input voltage, the noise margin low (NML = Vol – Vil) was 0.449 VDD at VDD = 2.1 V. A high input voltage has a noise margin high (NMH = Vih – Voh) of 0.370 VDD at VDD = 2.1 V. Supplementary Fig. 1 shows the electrical characteristics of other inverters, where good signal inversion is also evident, and deviations among different devices are barely observed. Also therein, a maximum voltage gain of ~38 was recorded. The comparison between our work and other reported works in terms of channel type and performance is summarized in Table 2. Our inverter presents a similar level in voltage gain, transition voltage, power consumption, and VIN and VDD range compared to current FinFET inverters. All these results imply that high-quality Si-MoS2 hybrid CMOS inverters with stable and reproducible device performance were achieved by the proposed manufacturing process.

Fig. 5: Output characteristics of 3D Si-MoS2 complementary inverter.
figure 5

a Voltage transfer characteristics of the 3D CMOS inverter for power supply voltage (VDD) from 0.1 V to 2.1 V in 0.5 V steps. Peaks in the red curves indicate the corresponding voltage gain at different VDD. b Noise margin of a CMOS inverter. When the inverter was applied with a low input voltage, the noise margin low (NML) is 0.449 VDD (VDD = 2.1 V). When applied with a high input voltage, the inverter has a noise margin high (NMH) of 0.370 VDD (VDD = 2.1 V).

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Table 2 Comparison of the inverter performance in this work and other researchers’ works.
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Critical considerations concerning future M3D CMOS devices with 2D materials

In the proposed 3D inverter, additional layout electrodes were fabricated to interconnect two FETs after the device-to-device variability in 2D MoS2 FETs and Si FinFETs had been checked. However, these layouts required extra area for interconnection, which would cause a limitation to IC density in future heterointegration. To increase integration density, common gate electrodes and vertically stacked heterostructures with back-gated 2D FET are promising solutions. In this regard, large-scale, single-crystalline 2D materials growth and reliable transfer method have been demonstrated34,35, which are crucially important to boost the integration efficiency. The proposed process is expected to be utilized in future M3D heterostructures with large-scale 2D materials.

It should also be noted that 3D self-aligned device architectures with vertically stacked n- and p-FETs, recently achieved in semiconductor nanoribbon transistor stacks36, will be a potential next step for the proposed M3D heterointegration with 2D material transistors. In such kind of device, the gate-all-around (GAA) architecture promises improved electrostatic control of the channel, enhanced current per area, and further device scaling. The GAA multichannel transistor stacks via vertically stacking n- and p-FETs provide a promising way toward 3D CMOS heterointegrations with high integration density. Accordingly, 2D materials feature uniform and clean surfaces states that avoid strong scattering of the charge carriers, which makes 2D FET exhibit excellent electronic properties to the ultimate limit of miniaturization in the vertical direction. Therefore, 2D materials can be a basic material for multichannel stacked transistors or GAA structure36 in future advanced electronics13. Furthermore, 2D materials device via transfer methods can be fabricated with a low-temperature process, which may mitigate the thermal budget issue in 3D ICs BEOL process.

In summary, a monolithic 3D CMOS inverter was fabricated by vertically integrating a p-type Si FinFET with 20 nm fin width and an n-type MoS2 FET. To fabricate the MoS2 FET upon the Si FinFET while effectively maintaining the device performance of the Si FinFET, we chose to utilize a series of low-temperature processes, including spin coating, CMP, CHE, e-beam lithography, wet-transfer, and e-beam VD. Exclusively, to prevent damaging the MoS2 layer and tuning Vth voltage, e-beam VD was utilized in depositing the Al2O3 top-gate dielectric instead of ALD. Consequently, symmetrical characteristic curves have been observed between the MoS2 FET and the Si FinFET after changing the MoS2 FET’s control structure from back-gated to top-gated. Moreover, the on/off current ratio and the on-current of both transistors show similar levels, which imply a compatible performance between the two unique structured devices as needed for CMOS implementation. The fabricated 3D inverter exhibits evident signal inversion with a maximum voltage gain of ~38. This work not only proves that 2D material-based and Si-based transistors can be integrated compatibly to form a CMOS inverter, despite their intrinsically distinct band structures, but demonstrates a feasible manufacturing method to integrate 2D materials into 3D ICs.

Methods

Other details concerning the device fabrication

Atomic Layer Deposition (ALD) process was used to grow the HfO2 layer around the fin-shaped Si channel. The tetraethyl orthosilicate (TEOS) passivation layer was applied via spin-coating. Al/Cu and Ni/Ti metal electrodes were deposited using a sequence of processes, namely the e-beam lithography, e-beam vapor deposition, and photoresist lift-off in such order. Likewise, a sequence of processes was used to perform the contact hole etching step, consisting of e-beam lithography, etching, and e-beam vapor deposition.

Electrical measurements on the FET devices

Electrical characterizations were performed via three-terminal I-V measurement using a semiconductor analyzer (Keithley model 2636B). The measurements were conducted at room temperature and under ambient atmosphere.

Optical characterization of the monolayer MoS2

Raman and photoluminescence (PL) measurements were conducted via an integrated confocal optical microscope system with a spectrometer (Kymera 328i, Andor). The light source is a 532 nm continuous wave laser operated at 14.5 mW for Raman and 150 μW for PL measurements (with 100×, N.A. = 0.9 objective lens), respectively. All measurements were conducted at room temperature.