Introduction

The development of deep neural networks (DNNs) has drawn attention worldwide owing to their varied applications and remarkable performance in image classification, object detection, and voice recognition1,2,3. From the hardware implementation point of view, executing a DNN algorithm requires numerous multiplications and additions (MACs) that consume large amounts of energy and computation time. For example, popular DNNs, such as LeNet-54, AlexNet5, and VGG-196 have weights of approximately 60,000 to 1 billion. Those weights are multiplied with 0.03~1.25 Mbytes of input feature maps, and the multiplication results are accumulated in the DNN process. In addition to the large computational burden, moving a large number of weights and input feature maps in the conventional von Neumann architecture requires a dominant portion of the total system energy. Recent reports show that the data movement consumes more than 2 times of energy compared to computing energy7. To relieve the energy burden due to data movement, in-memory computing (IMC), which can reduce data movement by performing MAC operations inside memories, has been actively studied8,9,10. In particular, memristor crossbar-based IMC can significantly reduce data movement, as a memristor can store large amounts of data, and matrix-matrix multiplications can be performed in the memristor crossbars with a small computational energy overhead11,12. Moreover, owing to the non-volatile nature of the memristor, the amount of leakage energy is remarkably reduced because the weight value remains constant for a long time even if the hardware is powered off. In this regard, numerous studies based on memristors have been reported, elaborating on their potential to be utilized as artificial synaptic emulators with various neuromorphic properties, such as long-term plasticity (LTP), short-term plasticity (STP), spike-timing-dependent plasticity (STDP), and spike-rate-dependent plasticity (SRDP). However, they have limitations concerning higher-level architectures for emulating biological synapses13,14,15,16,17. The development of memristor devices with synaptic functions and neural network simulation can enrich recognition functions, reduce hardware complexity, and realize highly efficient and accurate neural network computing.

Two-dimensional (2D) materials have been extensively utilized for building numerous electronic devices, such as thin-film transistors (TFTs), two-terminal diodes, and two-terminal resistive switching memristors18,19,20,21,22. Specifically, memristors have emerged as next-generation storage devices because of their complex electronic function implementations in both the lateral and vertical forms with high-performance memory properties18,22. With increasing interest in low-voltage operated memristors the vertical structure of memristors, in which a 2D material layer is sandwiched between the top and bottom electrodes, has attracted significant attention; the vertical structure reduces the interelectrode distance (nanometers), achieving lower operating voltages (1–10 V) compared with planar-structured memristor22,23,24,25. To date, several studies have reported on 2D material (i.e., MoS2, WS2, and MoSe2)-based memristors with good memory performance for nonvolatile memory applications with less uniformity and stability26,27,28,29,30,31. However, in previous studies, the active layers, more specifically, 2D material-based memristive devices have not been fully explored for use in high-scale architectures. Therefore, an easy and simple strategy for building highly scalable uniform memristive devices is required not only for a large-area grown 2D films but also for artificial electronic synapse implementations.

In this work, we introduce the novel concept of multilevel electronic synapses based on synthesized trilayer MoS2 memristors. The trilayer MoS2 was synthesized using a two-step process with a combination of radio-frequency (RF) sputtering and chemical vapor deposition (CVD) and directly grown onto the patterned bottom electrode. The proposed memristor has achieved high memory operations with stable endurance (~ 500 cycles) and good retention (~ 104) properties using the scalable uniform memory operations of 4 × 4 crossbar MoS2 based memristive array. Motivated by neuromorphic applications, we have further demonstrated memristive synapses based on trilayer MoS2 memristors, successfully mimicking synaptic neuromorphic functions (electric potentiation and depression with multi-level measurements) with 98.55% recognition accuracy using DNN simulation and providing an innovative platform for neuromorphic applications in the field of electronics.

Results

Synthesis and characterization of large-area grown uniform trilayer MoS2 film

A large-area MoS2 film was grown via a two-step process consisting of RF magnetron sputtering deposition and thermal CVD sulfurization (Supplementary Fig. 1a, b, for more details see Experimental Section). A thin Mo film was first deposited onto a SiO2/Si substrate via RF magnetron sputtering and then sulfurized with H2S gas in a thermal CVD chamber. Supplementary Fig. 1c shows the temperature profile according to the time of gas injection. Figure 1a shows a bare SiO2/Si substrate (left) and an as-grown MoS2 film on a SiO2/Si substrate (right) with a size of 3.5 × 3.5 cm. The MoS2 film exhibited a uniform blue color throughout the substrate. In addition, the optical microscope image in Fig. 1b shows that the MoS2 film is continuous over a large area, without any islands or cracks. Note that scratches were intentionally introduced on the MoS2 film to increase the color contrast of the image. The thickness of the MoS2 film was characterized using atomic force microscopy (AFM). As shown in Fig. 1c, the thickness of the MoS2 film was measured to be ~2.1 nm, indicating that the film consists of three layers32.

Raman spectroscopy was used to characterize the crystallinity and number of MoS2 layers. As shown in Fig. 1d, the Raman spectrum of the MoS2 film contains two peaks: an in-plane $${{{\mathrm{E}}}}_{2{{{\mathrm{g}}}}}^1$$ mode located at 383.5 cm−1 and an out-of-plane (A1g) mode located at 406.9 cm−1 33. The difference between the frequencies (∆k) of the two modes can be used to identify the number of layers of MoS2 film; this difference was determined to be 23.4 cm−1, indicating a trilayer MoS234. The Raman results agree with the previously reported values of mechanically exfoliated MoS2, which suggests that our MoS2 film has a high crystallinity. To confirm the thickness uniformity of the large-area MoS2 film, Raman mapping was performed over an area of 20 × 20 µm, as shown in Fig. 1e, f. The color distributions in the Raman mapping images are uniform, which indicates the high crystallinity and uniformity of the grown trilayer MoS2 film on the microscale.

To study the chemical state and elemental composition of the MoS2 film, X-ray photoelectron spectroscopy (XPS) was used to analyze the surface. Figure 1g, h show the core-level XPS spectra of Mo 3d and S 2p, respectively, including deconvolution curves. In the Mo 3d spectrum, the two intense peaks located at 229.9 and 233.0 eV are attributed to the doublet of Mo4+ 3d5/2 and Mo4+ 3d3/2, respectively, in agreement with Mo-S bonding, indicating the existence of 2H-MoS235,36. In addition, two small peaks located at 233.1 and 236.3 eV belong to the doublet of Mo6+ 3d5/2 and Mo6+ 3d3/2, respectively, corresponding to Mo-O bonding associated with MoO337. The atomic fraction of Mo6+ 3d in the grown MoS2 film was estimated to be 16.88%, and is expected to have been generated during the exposure of the MoS2 film to air (Supplementary Table 1). As previously reported, the Mo4+ 3d peaks of 1T-MoS2 or metal Mo exhibit a binding energy of 0.9–1.0 eV, which is lower than that of 2H-MoS238. However, no additional peak is observed at the low binding energy of approximately 229.0 eV, indicating that the sputtered metal Mo is fully sulfurized and transformed into 2H-MoS2 without any residual metal Mo. In the S 2p spectrum, two peaks at 162.5 and 163.7 eV are attributed to the doublet of S2− 2p3/2 and S2− 2p1/2, respectively35,36,38. These two peaks also correspond to 2H-MoS2, which further confirms the crystal structure of the grown MoS2 film. The atomic fraction of Mo4+ 3d in the MoS2 film was as high as 83.12%. Moreover, the atomic ratio between S2− 2p and Mo4+ 3d is approximately 2.19, which indicates a S-rich MoS2 with good crystallinity.

The crystalline and layered structures of the grown MoS2 films were investigated via TEM. In Fig. 1i, the low-magnification transmission electron microscopy (TEM) image over an area of 11 × 11 µm shows a large-area uniform film. Moreover, high-resolution TEM (HRTEM) and the corresponding fast Fourier transform (FFT) patterns are shown in Fig. 1j, k, respectively. The FFT pattern shows a ring shape, suggesting that the MoS2 film has a polycrystalline structure. The composite false-colored image was constructed by overlaying the HRTEM image with a color code acquired from the crystallographic orientations presented in the FFT pattern in Fig. 1k. The crystalline domain size of the grown MoS2 film was determined to be 20–50 nm. This value is larger than that of previously reported MoS2 produced by sputtering39,40. The cross-sectional TEM image shown in Fig. 1l reveals that the MoS2 film consists of three layers. The measured average interlayer spacing is approximately 0.63 nm, which agrees with the theoretical values, indicating the high crystallinity of the grown MoS2 film32.

Memory measurements of direct grown MoS2 based 4 × 4 cross memristor array

A high-volume scalable synthesis of the MoS2 layer was proposed to check the uniformity of the device performance. Therefore, a (4 × 4) crossbar memristor array based on MoS2 active material was fabricated on a single substrate (schematic view is shown in Fig. 2a), where the ultra-thin MoS2 film was sandwiched between bottom electrodes (BEs) of Pt (thickness of 50 nm) and top electrodes (TEs) of Ag (thickness of 50 nm), whereby both electrodes were patterned using a conventional lithography process (a real image of fabricated (4 × 4) crossbar memristor array, shown in Fig. 2b). A three-dimensional 3D section view of the proposed single MoS2 based memristor is shown at the bottom of crossbar array (Fig. 2b), defining the proposed MoS2 based memristor stacking structure. The TEs and BEs of the proposed crossbar (4 × 4) array define nodes of source lines (SLs) and Bit lines (BLs), respectively, shown in the schematic layout of Fig. 2c. Here, the atomic layer of the MoS2 film was directly synthesized onto the patterned BEs using a two-step growth process. A detailed description of the device and the fabrication process is provided in the experimental section. The current-voltage (I − V) characteristics of the proposed single crossbar memristive device were analyzed and bipolar non-volatile memory switching properties were observed at a set voltage (Vset) of 0.35 V and a reset voltage (Vreset) of −2.2 V at a sweep voltage range from −2.5 V to 2 V under ambient conditions, as shown in Fig. 2d. Although the previous reports suggest the volatile behavior due to higher thickness, the present CVD grown large-area MoS2 is of sub-3 nm, which could be a reason for the non-volatile nature of the memory obtained41. The active area of the proposed device is defined by the width of the TE and BE, which is approximately 10 × 10 µm. Given this, it has been attributed that when the positive bias voltage is applied to the Ag electrode, a conductive filament (CF) is formed due to the Ag diffusion from Ag-metal to Pt-metal in which Ag atom, overcoming the energy barrier of crystalline trilayer MoS2 film, causing the memristor to switch from high resistance state (HRS) to low resistance state (LRS) (set). To transit from LRS to HRS (reset), positive bias voltage to negative bias voltage switching is required which collects the Ag atom in the filament back to Ag-metal, rupturing of filament due to the interfacial energy minimization, overall reducing the Ag filaments via controlled diffusion length of Ag42,43. Overall, the mechanism of the proposed memory operation is defined in the schematic layout of Supplementary Fig. 2. Furthermore, the key merit figures of the memory properties, endurance, and retention operations were analyzed. Consecutive I-V sweeps (~ 500 cycles) with a voltage range of −2.5 V to 2 V were applied to investigate the endurance of the proposed MoS2 based memristor and the results show a very stable and uniform high resistance state (HRS) and a low resistance state (LRS) at a read voltage of −1 V with a reset voltage of −2.5 V, as shown in Fig. 2e. The obtained stable and memristive operations confirmed the uniform distribution of the MoS2 film without any failures in the conductive filament (CF) formations and a thin atomic layer of MoS2 film (thickness of ~2.1 nm) for operation at a lower voltage without any failure or breakdown, respectively. Next, the retention property of the proposed MoS2 based memristor was measured for 104 s at a read voltage of −1 V with a Vreset of −2.5 V, revealing no significant effect of the HRS and LRS states on the device during the measurement time, which indicates that the long-term retention can be expected to exceed one-year using extrapolation in the HRS and LRS scales, as shown in Fig. 2f. Further, the retention up to 104 s of the proposed device was measured at temperature of 50 °C, revealing the high robustness of the device (Supplementary Fig. 3).

Next, the I-V sweep measurements of MoS2 based crossbar memristor array (4 columns, 4 rows, 16 devices) were measured with a similar active area (width of 10 µm) on a single substrate under ambient conditions. The I-V sweep curves of the proposed memristor array (16 devices) exhibited a uniform bipolar switching curve with stable HRS and LRS behavior, as shown in Supplementary Fig. 4, demonstrating the proposed direct grown large-area MoS2 deposition method can contribute to device-to-device integration. A reliable and uniform Vset (0.5 ± 0.2 V) and Vreset (−1.6 ± 0.6 V) were observed, described in a statistical form in Fig. 2g, h, respectively, enabling a new platform for scalable memristor devices based on directly grown MoS2 film in the field of electronics.

To confirm the reproducibility of the proposed memristor device, additional five different memristive devices were fabricated with Ag/MoS2/Pt structure and the results consistently exhibit bipolar resistive switching behavior in terms of I-V and set/reset voltage curves, shown in Supplementary Fig. 5a, b, respectively, reveal stable and consistent responses in terms of set and reset voltages in the range of 0.2–0.67 V and −1.5 to −2.2 V, respectively. Furthermore, the proposed MoS2 memristor device performance is compared by previously reported MoS2 based memristor with respect to various device parameters (endurance, retention, deposition method, bottom electrode/substrate, and scale), revealing a stable and reliable memory performance on large-area integration (Supplementary Table 2). The obtained memristive consequences are worth noting: (1) a uniform distribution of the synthesized MoS2 film is extremely important for obtaining stable and well-defined memristive operations without any failure in the CF formations and (2) the thin active layer of MoS2 with a thickness of ~2.1 nm enables the achievement of low-voltage switching operations (at lower than 2.5 V).

Deep neural network simulation implementation on MoS2 based 4 × 4 cross memristor array

To simulate DNN, the Modified National Institute of Standards and Technology (MNIST) database was used as dataset, and the recognition accuracy was measured using Pytorch. Figure 4a shows the baseline convolutional neural network (CNN) model used in the simulation, which consists of 3 convolutional layers and 2 fully connected layers. The input data and weight parameters are quantized to 8 and 6 bit, respectively. As a single memristor represents a 3 bit binary number, two memristor devices were used to represent a 6 bit weight, and the most significant bits (MSBs) and least-significant bits (LSBs) were merged after they were quantized in the ADC. In addition, training of the model was performed for 30 epochs and the convolutional layers conducted convolution operations between the input feature map and kernel, as depicted in Supplementary Fig. 9, with a description of the training model (Experimental Section, Simulation of convolutional neural network). As shown in Fig. 4b, when a non-zero input enters the crossbar, the corresponding source lines (SLs) are driven by the VDD. Then, the current, whose strength is determined by the memristor conductance in each column-line flows from SLs to the memristors and is summed in bit line (BL). The summed current is determined by the binary inputs and weights stored in the memristor. Figure 4b also presents the overall architecture of the proposed memristor crossbar which implements the conversion of the summed current into a digital output (equation). The summed current in the BL node is converted to an analog voltage, and the voltage is maintained using a sample and hold circuit. Then, the ADC is used to convert the analog voltage to a digital output value. More specifically, Fig. 4c shows the MAC operations performed by the memristor crossbar using current summation in which a Complementary metal–oxide–semiconductor (CMOS) transistor is attached to each memristor as a selector. The proposed memristor can represent eight levels based on the conductance value, as shown in Fig. 3e, f. The conductance values of the proposed memristor are presented in Supplementary Table 3, displaying the eight selected conductance values of the potentiation and depression processes of the artificial electronic synaptic device. Figure 4d shows the waveform example to show the reliability of the MAC operation performed in an 8 × 8 crossbar array designed by Virtuoso and simulated by HSPICE with 28 nm CMOS technology. In the crossbar array, SL[0]–SL[7] are connected to eight memristors with different conductance levels (from HRS to LRS). When only one SL is activated in turn from SL[0] to SL[7] every 2 ns, the BL voltage increases with an increase in the conductance of the accessed memristor. However, the non-ideal characteristics of the memristor device, such as nonlinear conductance and device variation, disrupt accurate MAC operation, which leads to a recognition accuracy drop in the neural network. Despite the non-ideal characteristics of the proposed memristor, the nonlinearity (NL)12 of the potentiation conductance of the proposed memristor is calculated as 0.82, which enables a linear increase in the BL voltage, as shown in Fig. 4d. Furthermore, the nonlinearity analysis method is described in Supplementary Section 1. Note that memristor device variations are considered, and the conductance variations of the potentiation and depression characteristics of each device were measured by manufacturing several devices. Based on circuit simulation data, we evaluated the recognition accuracy when neural network hardware was implemented with the proposed memristor-based crossbar array. Please note that the memristor device variations are considered in the accuracy evaluation, and the conductance variations of the potentiation and depression characteristics of each device were measured using five fabricated memristor devices. Figure 4e shows the recognition accuracies in a software-based neural network (SW-NN) and the proposed memristor-based hardware neural network (HW-NN). Compared with SW-NN, which is assumed to have no error, there is an accuracy drop in the HW-NN owing to device variations and conductance nonlinearity. However, the effect of the MAC operation error is minor because of the low NL ( < 1), as mentioned before. In addition, even with MAC operation errors, most MAC results fall within adjacent levels, which leads to a negligible accuracy drop. The recognition accuracy of the HW-NN was 98.55%, whereas that of the SW-NN was 99.41%. Furthermore, the proposed MoS2 memristor device is compared with previous reported MoS2 memristor devices in terms of neural computation such as neuromorphic measurements, computational method, and recognition accuracy, revealing a high performance of the proposed MoS2 memristor device, described in Supplementary Table 2. The high accuracy of the HW-NN implemented in the proposed memristor device implies its potential for accurate neural network computing.

Discussion

In summary, an artificial electronic synaptic device was designed and fabricated for the emulation of memory dynamics based on a trilayer MoS2 memristor. Herein, the trilayer MoS2 film was synthesized by a simple combinational method of sputtering and CVD processes and directly grown onto the patterned bottom electrode of Pt metal. Moreover, the material characteristics were confirmed using various techniques such as AFM, XPS, TEM, and Raman spectroscopy. This simple memory device exhibits high memory operations with a high endurance (up to 500 cycles) and excellent retention (>104) along with highly uniform characteristics for the 4 × 4 memristor array. This simple synaptic device can realize synaptic dynamics such as potentiation and depression functions with reliable linearity in the learning and forgetting properties. We demonstrate an artificial neural network simulation of the MoS2 memristor device, exhibiting a recognition accuracy of 98.55%, which is close to the ideal recognition of 99.41%, thus providing a new platform for memristor devices for accurate neural network computing.

Methods

Synthesis and fabrication of the proposed memristor

P-type boron-doped Si substrates covered with 300-nm-thick SiO2 were used as substrates. Before device fabrication and MoS2 film growth, the SiO2/Si substrates were cleaned for 10 min by ultrasonication in acetone, isopropyl alcohol, and deionized water. Conventional photolithography was used to construct the bottom electrodes. Pt (50 nm) was deposited via electron beam deposition and patterned via a lift-off process using a photoresist remover. To synthesize the MoS2 film on the Pt electrode, a Mo film was deposited via a magnetron sputtering system using a 101.6-mm-diameter Mo target (99.99%). The chamber base pressure was maintained below 3 × 10−6 Torr after the substrate was loaded. The working pressure was maintained at 10 mTorr with an Ar flow of 100 sccm. Before deposition of the Mo film, the Mo target was pre-sputtered for 10 min to remove its oxidized surface and stabilize the plasma. The Mo film was deposited at room temperature with an RF power of 150 W for 180 s. The as-deposited Mo film was then loaded into a 2-inch CVD chamber for sulfurization. The CVD chamber was pumped to achieve a low vacuum, and Ar was injected at a flow rate of 50 sccm. The furnace temperature was ramped up to 750 °C within 30 min and maintained for 15 min. A gas mixture of H2S (1 sccm) and H2 (5 sccm) was added to the chamber when the temperature reached 300 °C. An annealing process was carried out at 1000 °C for 1 h under a H2S (1 sccm) and Ar (50 sccm) atmosphere. After annealing, the CVD furnace was rapidly cooled to room temperature under an Ar atmosphere at a flow rate of 50 sccm. Finally, 50 nm Ag was deposited as a top electrode via electron beam deposition and patterned via the lift-off process.

Material characterization

Optical microscopy (BX51M, Olympus Co.) was used to examine the surface of the MoS2 film synthesized on the SiO2/Si substrate. The thickness of the trilayer MoS2 film was measured using AFM (XE7, PSIA Co.) in the non-contact mode. Raman spectra were obtained using micro-Raman spectroscopy (ALPHA300, WITec Co.) with a 532 nm excitation laser. Raman spatial mappings were measured using a micro-Raman system (FEX, NOST) with laser excitation at 523 nm. The step for Raman mapping was 0.5 mm. Raman analysis was performed under ambient conditions, and the power of the laser line was below 1 mW. XPS spectra were characterized using a Theta Probe AR-XPS System (ThermoFisher Scientific) with Al Kα X-ray radiation (1496.6 eV). For TEM observation, the MoS2 film was transferred onto a Cu grid with a lacey carbon support film. The cross-sectional TEM imaging sample was fabricated using a focused ion beam system (NX2000, HITACHI). Atomic images were obtained using a TEM (JEM ARM 200 F, JEOL) with an accelerating voltage of 80 kV.

Electrical measurements

The memory operations were measured using a semiconductor characterization system (Keithley, 4200 SCS). The synapse measurements were characterized using a pulse-modulation unit system.

Simulation of convolutional neural network

The accuracy evaluation of the memristor-based crossbar array was performed on the Pytorch platform. The model constructed for the neural network simulation consisted of three convolutional layers and two fully connected layers. The 28 × 28 pixels of the MNIST digit patterns were converted into grayscale numbers and entered as an input to the first layer. The MAC operation was performed in each layer, and the model inferred the input number based on the output value of the previous layer. Training of the model was performed for 30 epochs, and the training parameter settings were as follows: learning rate: 1e − 3, activation function: ReLU, kernel size: 3 × 3, stride: 1, input: 8 bit quantized, weight: 6 bit quantized. The training process was applied to 60,000 images of the MNIST dataset for every epoch, and 10,000 images were tested with the trained model to evaluate the recognition accuracy. At the inference stage, we substituted the MAC operation error rate by the HW-NN recognition accuracy, which was calculated by customizing the convolution layer and fully connected layer in Pytorch.