Fig. 3: Electrical characterization at room temperature (T = 300 K) of a representative WSe2 FET and the WSe2/SnSe2 heterojunction device fabricated on the very same flake. | npj 2D Materials and Applications

Fig. 3: Electrical characterization at room temperature (T = 300 K) of a representative WSe2 FET and the WSe2/SnSe2 heterojunction device fabricated on the very same flake.

From: WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

Fig. 3

a Transfer characteristic in semilogarithmic scale of the WSe2 FET for increasing values of the drain bias. The ON/OFF current ratio is larger than 105 and the minimum subthreshold slope ranges from 80 to 110 mV per decade. Inset: transconductance as a function of the gate bias. b WSe2 transconductance efficiency as a function of the device output current. c Subthreshold slope vs drain current for the MOSFET under different applied drain to source bias. The width of the WSe2 FET is 2 µm. d Transfer characteristic in semilogarithmic scale of the WSe2/SnSe2 Tunnel FET for increasing values of the drain bias. The threshold voltage is shifted to more negative values with respect to the WSe2 FET, while the turn-on slope is improved. Inset: transconductance as a function of the gate bias. e Heterojunction FET transconductance efficiency as a function of the device output current. For all the investigated drain to source biases, the peak transconductance efficiency exceeds the fundamental 40 V−1 limit characterizing MOSFET devices. f Subthreshold slope vs drain current for the TFET, showing room temperature subthermionic point swing for all the applied drain biases.

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