WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Several evidences of room temperature band-to-band tunneling (BTBT) have been recently reported, but only few tunneling devices have been proven to break the Boltzmann limit of the minimum subthreshold slope, 60 mV per decade at 300 K. Here, we report the fabrication and characterization of a vertical p-type Tunnel FET (TFET) co-integrated on the same flake with a p-type MOSFET in a WSe2/SnSe2 material system platform. Due to the selected beneficial band alignment and to a van der Waals device architecture having an excellent heterostructure 2D–2D interface, the reported tunneling devices have a sub-thermionic point swing, reaching a value of 35 mV per decade, while maintaining excellent ON/OFF current ratio in excess of 105 at VDS = 500 mV. The TFET characteristics are directly compared with the ones of a WSe2 MOSFET realized on the very same flake used in the heterojunction. The tunneling device clearly outperforms the 2D MOSFET in the subthreshold region, crossing its characteristic over several orders of magnitude of the output current and providing better digital and analog figures of merit.


INTRODUCTION
The scaling of transistors has been the driving force behind the digital revolution over the last decades, enabling enhanced switching frequency, higher density, decreased cost and enormous increase in computational power 1 . However, several fundamental and technical challenges potentially jeopardize the performance of aggressively scaled CMOS technology nodes 2,3 . In particular, the power supply scaling, fundamental in order to reduce the dynamic power consumption of a transistor, is currently halted because of the fundamental physical limit of 60 mV per decade for the subthreshold slope of devices relying on thermionic injection. Voltage scaling at constant gate overdrive results in an unacceptable increase of the OFF state current and consequently of the static power consumption 4 .
In order to overcome the Boltzmann limit to the subthreshold slope, it is necessary to rely on a different carrier injection mechanism [4][5][6] . Tunnel FETs (TFETs), for instance, exploit band-toband tunneling (BTBT) so as to achieve subthermionic subthreshold slope and potentially outperform CMOS in the subthreshold regime 4,7 . Promising performance has been obtained in silicon, germanium, III-V and heterojunction TFET, with sub 60 mV per decade slope 4,8,9 . However, the difficulties of obtaining sufficiently sharp doping profiles or material interfaces pose incredible challenges to the realization of tunneling switches exploiting conventional three-dimensional semiconductors. Indeed, band-tail states and trap assisted tunneling paths can drastically degrade the turn-on slope of such devices 10,11 .
In this contest, two-dimensional (2D) materials are promising candidates for the realization of high performance TFETs, providing both a huge variety of electronic properties and the possibility of assembling atomically sharp van der Waals heterojunctions 12 . Several demonstrations of BTBT in 2D-based heterojunctions have been recently reported, with negative differential resistance (NDR) observed in the output characteristic at room or cryogenic temperatures [13][14][15][16][17][18] . However, few 2D TFETs were able to break the 60 mV per decade limit at room temperature 19,20 . Several materials have been investigated by either atomistic simulations or experimental studies. The onset of BTBT has been reported in WSe 2 /MoS 2 , BP/SnSe 2 , BP/MoS 2 , Ge/ MoS 2 and WSe 2 /SnSe 2 heterojunctions 13,[15][16][17][18][19][20][21] . This latter material system has attracted particular interest because of the predicted broken or nearly broken gap band alignment and the peculiar electronic properties of these two members of the transition metal dichalcogenide (TMDC) family. WSe 2 is an intrinsic semiconductor that exhibits both electron and hole conduction with relatively high carrier mobility 22 . Suppression or enhancement of one of the two conduction branches can be effectively obtained exploiting electrostatic doping [23][24][25] . This feature, unusual for TMDC 2D materials that are usually unipolar with dominant electron conduction, presents this material as one of the best candidate for the realization of a single material 2D CMOS technology. Conversely, SnSe 2 is degenerately n doped and exhibits an extremely low sensitivity to electrostatic control 26,27 . Several WSe 2 /SnSe 2 heterojunction devices exhibiting NDR have been recently reported, and an n-type TFET with minimum subthreshold slope (SS) of 50 mV per decade was demonstrated 19 .
Recently, we reported at IEEE IEDM 2019 a preliminary WSe 2 / SnSe 2 p-type TFET with room temperature subthermionic subthreshold slope, demonstrating the potential of this material system for the realization of tunneling devices with good characteristics 28 . Here, we report new data confirming the subthermionic values for the subthreshold slope derived from both source and drain currents with small hysteresis. Moreover, we report first principle derivation of the expected band alignment at the junction obtained by density functional theory (DFT) calculations. We then discuss the possible BTBT mechanism matching our experimental findings. Finally, we provide a direct comparison of the heterojunction TFET and the built-in WSe 2 MOSFET in terms of both digital and analog figures of merit of the out best device. We show that the WSe 2 /SnSe 2 TFET outperforms its WSe2 counterpart over several orders of magnitude of the output current both for analog and digital applications.

RESULTS AND DISCUSSION
Heterojunction band diagram The structure of the fabricated WSe 2 /SnSe 2 heterojunction devices is shown in Fig. 1. In order to accurately model the band alignment of the heterostructure, VASP 29 , a density functional theory tool, is employed. A supercell containing six layers of each material is constructed by applying a relative rotation of 30°and a small strain of 0.22 % to both layers, resulting in a hexagonal cell containing four units of WSe 2 and three units of SnSe 2 in their respective layers. This configuration (30°+ 0.22% strain) was chosen because it minimizes the size of the supercell required to perform DFT calculations. It should be noted that the strain value is kept very small and the rotation angle is not known experimentally. The results are expected to marginally depend on this parameter. Electronic structure calculations are performed using the generalized gradient approximation (GGA) of Perdew, Burke and Ernzerhof (PBE) 30 , with a 11 × 11 × 1 Monkhorst-Pack kpoint grid and a 500 eV plane-wave cutoff energy. The convergence criteria are set to less than 10 −2 eV Å −1 force acting on each ion and a total energy difference smaller than 10 −3 eV between two subsequent iterations. van der Waals interactions are included through the DFT-D3 method of Grimme 31 . The resulting computed band structures of WSe 2 and SnSe 2 are shown in Fig.  1b, where the bands have been colored to indicate the material from which they originate. A closer look at the derived band alignment is provided in Fig. 1c, that shows a type III, broken gap with an expected energy overlap of 26 meV. Figure 1d represents a qualitative band diagram of the WSe 2 / SnSe 2 heterojunction obtained starting from reported results on similar heterostructures assembled with multilayer WSe 2 and thicker SnSe 2 flakes 13 . As confirmed by our DFT calculations, at the equilibrium the band alignment is of type III, resulting in a nonzero energy overlap between SnSe 2 conduction band and WSe 2 valence band. By applying a positive drain bias to the WSe 2 contact, electrons can tunnel from SnSe 2 to WSe 2 providing a BTBT conduction path. A negative bottom gate voltage determines an upward shift of WSe 2 bands, resulting in an increase of the energy overlap and an enhanced tunneling current. Therefore, we expect our three terminal heterojunction devices to exhibit a tunneling current at positive drain to source voltage with negative bottom gate bias.

Device fabrication
The three-dimensional schematic view of the final heterojunction device is shown in Fig. 1a, which consists of a back gated WSe 2 / SnSe 2 heterojunction with Pd Schottky contacts deposited on each side of the junction. The first fabrication step is the deposition by atomic layer deposition (ALD) of 50 nm layer of hafnium oxide (HfO 2 ) on a Si wafer. The bottom gate electrode is then defined by electron beam lithography (EBL) on a MMA/ PMMA bilayer and lift-off of 50 nm of tungsten (W). The gate stack is then completed by a second ALD deposition of 10-nm-thick HfO 2 . WSe 2 flakes have been mechanically exfoliated directly on the patterned substrate starting from commercially available bulk samples. In order to form the junction, SnSe 2 flakes were first exfoliated on a poly(dimethylsiloxane) (PDMS) transparent substrate and then deterministically transferred on previously selected WSe 2 samples 32,33 . The source and drain contacts were deposited by lift-off of a Cr/Pd stack (5/50 nm) after a second EBL Electrical characterization All the electrical measurements have been performed at room temperature and ambient conditions. The WSe 2 contact is always biased as the drain of the heterojunction device. As a first step, we characterized the electrical properties of individual SnSe 2 and WSe 2 flakes. The double-sweep transfer characteristic, drain current versus the gate voltage, I D -V G , and the output characteristic, drain current versus the drain voltage, I D -V D , of a representative SnSe 2 FET is reported in Supplementary Fig. 1. As expected, given the degenerate n doping typical of this 2D material, the gate bias has a very limited capability of modulating the conduction in the channel 27,34 , that cannot be depleted of electrons for the investigated range of voltages resulting in a ON/ OFF current ratio lower than two. The low drain voltage region of output characteristic shows an ohmic contact is achieved between the Pd electrodes and multilayer SnSe 2 flakes.
The transfer characteristic, drain current versus gate voltage, I D -V G , of a representative WSe 2 FET measured at different drain biases is reported in Fig. 3a. The device, whose channel is 2 µm wide, exhibits p-type polarity with ON/OFF current ratio larger than 10 5 . The hole mobility can be extracted applying the Y function method (see Supplementary Fig. 2) 35,36 . At V D = 500 mV, the carrier mobility is 1.8 cm 2 V −1 s −1 , comparable to reported results on similar devices 23 . The inset in Fig. 3a shows the transconductance of the device, g m , which saturates upon reaching the maximum value. The ratio of the gate transconductance and the drain current gives the transconductance efficiency, plotted in Fig. 3b for three values of the drain voltage. g m /I D is a fundamental parameter to evaluate the potential of a technology platform for analog applications 37 . Indeed, high transconductance efficiency values are fundamental for the design of high performance, low power consumption differential couples. In a MOSFET, the maximum value of the transconductance efficiency is physically constrained to be lower than 40 V −1 and the maximum value can be achieved operating the device in its weak inversion regime 38 . As shown in Fig. 3b, our WSe 2 pMOSFET achieves a g m /I D value comprised between 25 and 30 V −1 , comparable to advanced bulk Si FET [39][40][41][42][43] .
The potential of a technology to realize energy efficient, low voltage digital switches can be evaluated considering its subthreshold slope. A steep turn-on characteristic is fundamental to scale down the power supply, or to achieve higher current at lower gate voltage and, therefore, faster switching for the same gate bias. Figure 3c shows the subthreshold slope as a function of the output current for the three investigated drain biases. The minimum point value is 80 mV per decade and point slopes around 100 mV per decade are maintained also at V DS = 500 mV. Such results are better or comparable with the best reported back gated WSe 2 FETs 23,24,[44][45][46] . Figure 3d-f collects the corresponding results obtained measuring the WSe 2 /SnSe 2 heterojunction TFET based on the very same WSe 2 flake characterized as MOSFET.
Comparing the transfer characteristics of the two devices (Fig. 3a, d) under the same drain bias, it is clear that the heterojunction TFET exhibits lower I ON , lower I OFF , more negative threshold voltage and steeper turn-on characteristic than its built-in WSe 2 MOSFET. The OFF state current is limited by the gate leakage, while the relatively large tunneling resistance at the heterojunction interface likely fixes the current level in the ON state. The inset of Fig. 3d shows the transconductance of the heterojunction FET, from which it is possible to derive the transconductance efficiency curve, represented in Fig. 3e as a function of the drain current. The WSe 2 /SnSe 2 TFET exceeds, at room temperature, the (kT/q) −1~4 0 V −1 fundamental limit of MOSFET g m /I D analog figure of merit, for all the considered drain biases. Similarly, the subthreshold slope plotted as a function of the drain current shown in Fig. 3f exhibits point swing below the 60 mV per decade Boltzmann limit for all the three drain biases. In order to evaluate the impact of the gate leakage current on the estimation of the subthreshold slope, in particular for current levels close to the leakage floor as in our case, it is important to consider both drain and source transfer characteristics, and their relative subthreshold swings. Supplementary Fig. 3 reports the I D -V G and I S -V G characteristics, demonstrating that the numerical derivatives of both source and drain measured currents versus the gate voltage result in subthermionic values of the turn-on subthreshold slopes at room temperature. The transfer characteristics of a second couple of devices, again a WSe 2 MOSFET and its same flake WSe 2 /SnSe 2 TFET are reported in Supplementary Fig. 4. As discussed in our IEDM paper 28 , the output characteristic of this WSe 2 /SnSe 2 TFET shows a clear, gate tunable NDR region, that together with the measured subthermionic subthreshold slopes contributes to demonstrate the onset of the BTBT conduction path schematically described in Fig. 1d.
In order to discuss in more details the differences between the WSe 2 and the heterojunction FETs, it is useful to directly compare the relative transfer characteristics. Figure 4a collects the I D -V G curves of our reference TFET and its built-in MOSFET, both measured applying V DS = 500 mV. The TFET threshold voltage has been shifted so to match the MOSFET one and provide an easier correlation. The WSe 2 /SnSe 2 heterojunction device has both a lower I OFF current and steeper turn-on characteristic with respect to the WSe 2 FET (see the inset in Fig. 4a), crossing its characteristic at low current levels and indeed outperforming the MOSFET over almost three orders of magnitude of the output current. The minimum point subthreshold slope for the TFET is 35 mV per decade. As expected, the WSe 2 FET maintains a larger I ON current with respect to the tunneling device 4 , but the TFET current is indeed larger over the subthreshold region as highlighted in Fig.  4b, where the difference between the two devices current, normalized with respect to the WSe 2 FET current, is plotted as a function of the gate bias. This results in a larger transconductance over the corresponding bias window. Figure 4c shows the difference between the heterojunction TFET and its built-in MOSFET transconductances, normalized with respect to the MOS transconductance. In the subthreshold region, the WSe 2 /SnSe 2 TFET provides a transconductance boost of roughly 70 % over the WSe 2 FET. A direct comparison of the two same flake devices transconductance efficiencies is presented in Fig. 4d as a function of the output current. The WSe 2 /SnSe 2 heterojunction TFET not only overcomes the 40 V −1 analog efficiency limit at low current levels, but it consistently outperforms the WSe 2 FET, whose performance is comparable to long channel Si bulk MOSFETs 42,43 , over the entire subthreshold region. Conversely, for large drain current the MOSFET transconductance is larger, reflecting the higher I ON granted by the thermionic injection mechanism.
The reported results demonstrate the best reported experimental minimum subthreshold slope for 2D/2D heterojunction devices 13,18,19,21 , while maintaining an ON/OFF current ratio larger than five orders of magnitude and co-integrating on the same flake both the heterojunction tunneling device and the WSe 2 MOSFET.
The co-integration of MOSFET and TFET on the same flake paves the way for the realization of hybrid devices with dual transport mechanism that combine the advantages of each of these devices while not requiring any additional lithography and production steps. The possibility of co-integrating TFET and MOSFET in the same material system and technology platform has been explored thoroughly for silicon and III-V based devices 47-51 , but not yet in a true 2D/2D material system. Here, in Fig. 5a, we propose a new steep slope hybrid device, named dual transport (DT) FET consisting in the parallel connection of a WSe 2 /SnSe 2 heterojunction TFET and its built-in WSe 2 MOSFET. Such device could inherit the best figures of merit of a Tunnel FET and a MOSFET, a subthermionic subthreshold slope (dictated by a BTBT current) and a high on current (dictated by a thermionic current), respectively. The qualitative transfer characteristic of such a device is shown in red in Fig. 5a. In order to achieve such unique behavior, it is required that the TFET and MOSFET threshold voltages fulfill a particular condition, with the turn-on of the TFET before the MOSFET. In absolute values, |V Th,TFET | < |V Th,MOSFET | for p-type devices. Here, for simplicity, we consider the TFET threshold voltage extracted as the gate bias corresponding to the 60 mV per decade slope in the transfer characteristics, called the I 60 drain current. More precise engineering of this design condition, for the optimization of the DT FET figures of merit by taking the best of its composing device parts, would need the development of a physics-based compact model for such hybrid device, which was not the purpose of this work. For p-type devices, operated at negative gate voltages, enforcing this condition would grant that the p-type TFET controls the turn-on of the DT FET, while the pMOSFET intervenes for more negative back gate voltages providing the higher ON current.
For our fabricated devices, as discussed both in Fig. 3 and Supplementary Fig. 4, such condition is not fulfilled correctly, preventing us to match the condition for making an ideal dualtransport experimental device. Supplementary Fig. 5 shows the measured characteristic of the first experimental implementation of our DT FET based on the WSe 2 /SnSe 2 TFET and WSe 2 FET devices whose characteristic are collected in Supplementary Fig. 4. Because of the non-ideal relationship between the devices threshold voltages, the combined transfer characteristic follows more dominantly the MOSFET rather than the TFET at the turn-on.
In order to provide an estimation of the performance of such a device in an optimal design, we used the measured experimental transfer characteristic presented in Fig. 3 and we artificially shifted the TFET threshold voltage, as potentially possible by the use of metal contacts with different work functions. The resulting transfer curve is shown in Fig. 5b. As expected, provided that |V Th,TFET | < | V Th,MOSFET |, the DT FET turns on following the heterojunction tunneling curve and inherits both a steep transition and the higher thermionic I ON current of the MOSFET. Consequently, the proposed device exhibits better analog and digital figures of merit of the constituting devices. Figure 5c collects the transconductance efficiency of the three FETs: while not achieving the peak value obtained by the TFET, the DT FET exhibits a transconductance efficiency larger than the MOSFET one for the entire range of the output current, outperforming also the TFET at large drain currents. The evolution of the subthreshold slope follows a similar trend, as reported in Fig. 5d. Even if the DT FET proposed device does not reach a point subthreshold slope as small as the heterojunction TFET, it exhibits a much steeper turn on than the MOSFET and it outperforms the TFET at large current values.
The practical engineering of the WSe 2 MOSFET and WSe 2 /SnSe 2 threshold voltages can be obtained experimentally either by (i) changing the contact metal used for one of the two devices or (ii) depositing a top dielectric and top gate contact on the WSe 2 channel 24 . This second solution, while more challenging and cumbersome from a fabrication viewpoint, it would enable the

DISCUSSION
In this work, we reported co-integrated subthermionic 2D/2D WSe 2 /SnSe 2 tunnel FET and WSe 2 MOSFET realized on the very same flake. The device is fabricated by deterministic assembly of the van der Waals heterojunction on top of a tungsten/HfO 2 bottom gate stack. DFT calculations confirm that this heterojunction presents an optimal broken gap band alignment, resulting in room temperature subthermionic subthreshold slope and sizeable, gate tunable negative differential resistance observable in the output characteristic. A record low point subthreshold slope of 35 mV per decade at V DS = 500 mV has been demonstrated, while maintaining I OFF < 0.1 pA µm −2 and an excellent ON/OFF current ratio exceeding 10 5 . The fabricated pTFET clearly outperforms the built-in WSe 2 MOSFET, crossing its characteristic over several orders of magnitude of the drain current and providing better digital and analog performance in the subthreshold region. The demonstrated heterojunction device provides a new insight in the potential of 2D/2D systems for the realization of high performance steep-slope devices. Moreover, the possibility of cointegrating on the same flake both MOSFET and TFET with no increase in the process flow complexity paves the way to new hybrid device, such as the proposed DT FET, and circuit topologies able to harvest the steep TFET turn-on characteristic granted by the band to band tunneling conduction mechanism and the high MOSFET thermionic ON current.

Fabrication of WSe 2 /SnSe 2 bottom gated heterojunction devices
The starting substrate is a p doped silicon wafer. An insulation 50-nm-thick layer of HfO2 is deposited by atomic layer deposition (ALD). The bottom gate is obtained by the lift-off in acetone of 50 nm of sputtered tungsten after an electron beam lithography (EBL) step performed on a MMA/PMMA bilayer. The structure of the bottom gate is then completed by ALD of 10 nm of HfO 2 . The bulk WSe 2 and SnSe 2 crystals were purchased respectively from hq graphene and 2D semiconductors. WSe 2 flakes are directly exfoliated by scotch taping on the final substrate, and flakes with desired geometry, thickness and position are identified by optical microscopy. SnSe 2 is first exfoliated on a PDMS stamp that is then used c Transconductance efficiency of the DT FET and its constituting devices. While not reaching the peak transconductance value of the WSe 2 /SnSe 2 heterojunction, the DT FET maintains better performance of the MOSFET for all the output current range, outperforming also the TFET at large current values. d Direct comparison of the substhreshold slope as a function of output current for the DT FET and the base components. Similarly to the transconductance efficiency, the DT FET exhibits a minimum point subthreshold slope larger than the TFET, but it outperforms the WSe 2 MOSFET over the entire range of output current and maintains steeper characteristic than the heterojunction FET for large I D .
in combination with a micromanipulator and an optical microscope to deterministically transfer SnSe2 flakes on the previously selected WSe 2 flakes. The contacts to the heterojunction devices are obtained by evaporation and lift-off of a Cr/Pd stack (5/50 nm) after a second EBL step on MMA/PMMA bilayer resist. A third EBL step is performed to pattern a PMMA mask for the low power ion beam etching of the gate dielectric in selected areas in order to gain electrical access to the bottom gate contact.

Electrical measurements
All the reported electrical measurements have been performed at room temperature and ambient conditions using conventional semiconductor parameter analyzers and electrical probes. The WSe 2 contact is always biased as the drain of the heterojunction device.
Metrology AFM in contact mode for accurate thickness estimation and SEM have been performed after the electrical characterization, so to avoid contamination of the devices.

DATA AVAILABILITY
The raw data used in this study are available upon reasonable request to the corresponding author.