Introduction

Two-dimensional (2D) materials have attracted intensive attention because of their unique electronic structure and transport properties.1,2,3,4,5,6,7,8,9 Among 2D materials, indium selenide (InSe), a layered semiconductor made of stacked layers of Se-In-Se atoms, holds great promise because of its high intrinsic mobility and moderate electronic band gap (1.26 eV).10,11,12 Previous work has been performed to improve the mobility of InSe field-effect transistors (FETs) and other 2D material-based FETs.13,14,15 For instance, (1) Heterojunction structure,16 (2) high-k dielectric,1,13 (3) high-k encapsulation,17 and (4) Chemical and physical interface engineering15,18,19 have been used to enhance the carrier mobilities of 2D materials based FETs. However, in addition to the carrier mobility of FETs, electrical stability is another extremely important factor in ensuring device reliability in practical applications. Electrical instability is expressed mainly as threshold voltage shifts and carrier mobility degradation.20,21,22 Despite the considerable amount of theoretical and experimental research reported on 2D material-based devices, understanding of and improvements in their electrical stability are still in their infancy and remain a formidable challenge.

Earlier studies of InSe revealed that the performance of InSe FETs can be significantly influenced by the dielectric-2D semiconductor interface and the number of layers.13 At the dielectric-InSe interface, in addition to the intrinsic acoustic phonon scattering of multilayer InSe, interfacial Coulomb impurities (CIs), surface roughness, surface chemical properties and surface polar phonon scattering from the dielectric can all impact the carrier transport in InSe FETs. Both the carrier mobility and electrical stability of FETs fundamentally depend on the state of the dielectric-semiconductor interface, and the mechanism is complex. It was found that charge impurity scattering has important impact on transistor performance.3 Ghatak et al. claimed that Coulomb potential from trapped charges in the substrate is the dominant source of disorder in MoS2 field-effect devices.23 Researchers have investigated the influence of trapped charges on MoS2 transistor performance.24,25 However, an effective, convenient, and inexpensive approach is needed for improving both field-effect mobility and electrical stability of transistors, to expand InSe FETs to practical applications—highly sensitive and reliable sensors—for instance, for neuron action potential detection. Neural signal transmission is fundamental to diverse human behaviors, such as learning, cognition, motor action, emotion, perception, and consciousness.26,27,28,29,30 Moreover, improper functioning or abnormal neural signals are associated with numerous neurological disorders, such as high paraplegia, epilepsy, and Parkinson’s disease.31 Thus, highly sensitive and stable neural signal sensors capable of real-time and on-site detection are needed.32,33,34 High-performance InSe FETs are promising for realizing real-time, in situ neuron action potential detection, because of their high amplification factor and device flexibility when prepared on flexible substrates.

In this work, we employ PMMA-HfO2 dual-layer dielectric and back-channel encapsulation to effectively improve the electrical stability of InSe while maintaining its high mobility (~1200 cm2/V·s) under normal ambient conditions. The time-dependent and stress-dependent electrical stability was systematically analyzed. The hysteresis and threshold voltage shift in the working regime exhibit a negligible change (~0.2 V) over one month. Furthermore, density functional theory (DFT) was used to illustrate the basic physics and electrical stability mechanism of our newly configured InSe FETs. The calculation result shows that the increase in electron effective mass is relatively small when InSe forms the heterogeneous junction with PMMA compared to that for other dielectric substrates, which is consistent with the change in FET performance induced by different dielectric substrates. Based on the high electrical stability and field-effect mobility, InSe FETs allow us to conduct the real-time and in situ detection of frog sciatic action potential. The output signal of action potential was clean and traceable because of the transistors’ stable electrical performance. This valuable method could be easily expanded to other 2D materials and could open up new opportunities for these materials in high-performance sensing applications.

Results and discussion

The fabrication of our transistors started with deposition of a 30 nm HfO2 layer on a highly doped Si wafer by an atomic layer deposition (ALD) system at 150 °C and spin-coating of a 250 nm PMMA layer on HfO2, which function as the dual-layer dielectric (Fig. 1a, b). Supplementary Fig. 1 presents schematic diagrams of other InSe FET structures. A typical scanning electron microscopy (SEM) image of a multilayer InSe FET with a flexible PMMA and high dielectric constant HfO2 dual-layer dielectric together with PMMA back-channel encapsulation (PMMA/InSe/PMMA-HfO2 FET) is shown in Fig. 1c. The Raman spectrum (Supplementary Fig. 2a) of the multilayer InSe flakes shows peaks at 115, 178, and 228 cm−1, corresponding to the vibration modes of A1’(Γ21), E’(Γ13)-TO, and A1’(Γ31).35 The thickness of the InSe flake was determined by atomic force microscopy (AFM). Supplementary Fig. 2b shows a typical surface shape graph and AFM step scan image of an InSe flake (~35 nm). As shown in Fig. 1d, a high-resolution STEM image with an inset obtained by reverse Fourier transform presents the perfect crystallinity of the InSe flake with a hexagonal lattice spacing of 3.4 Å (0.34 nm).13 The chemical composition of the as-prepared InSe flake consists of indium and selenium at an atomic ratio of ~1:1, as measured by energy-dispersive X-ray spectroscopy (EDS). The elemental distribution within the marked area was characterized by using the composition mapping operation, indicating the homogenous distribution of indium and selenium over the sheet (Supplementary Fig. 2c–e). In the XRD pattern of the InSe crystal, which can be found in Fig. 1e, the five peaks correspond to (00I) (I = 2, 4, 6, 8, 12) without any other impurities, suggesting the high crystalline purity of the as-prepared InSe crystal. The dual-layer structure shows smooth physical contact under SEM (Fig. 1f). To extract the accurate electron mobility, the capacitor structure of high-k dielectric materials was fabricated, and the capacitance was measured as shown in Supplementary Fig. 3. It can be seen that a very high capacitance of COX = 1200 nF/cm2 could be obtained. The contact angles for water on different substrates are shown in Supplementary Fig. 4, indicating that the PMMA film is more hydrophobic than the other oxidized dielectrics, which is conducive to improving interface conditions by suppressing carrier scattering from chemical impurities. To ensure clean contacts and avoid possible contamination from photolithography, the source and drain contacts, Ti/Au (10/50 nm), were defined by a shadow mask and deposited by electron-beam evaporation. Then, PMMA was spin-coated and baked to encapsulate the back-channel of the InSe FET. PMMA encapsulation can effectively retard water and oxygen molecules penetrating, which improves electrical stability of InSe FETs in air. The Raman peak and intensity did not change significantly during the 20-day test, indicating that InSe was stable for a relatively long time in the case of PMMA encapsulation. Its Raman spectrum is shown Supplementary Fig. 5.

Fig. 1
figure 1

Schematics of InSe FETs and their fabrication process. a The fabrication protocol of the PMMA/InSe/PMMA-HfO2 FET. b Schematic diagram of a PMMA/InSe/PMMA-HfO2 FET. c Flat SEM image of an InSe FET. d High-resolution TEM image of an InSe flake and a fast Fourier transformation (FFT) image. e XRD pattern of an InSe flake. Inset: Schematic diagram of the InSe crystal structure. f Cross-sectional SEM image of the InSe FET dielectric layer

The IDS-VDS output characteristics and IDS-VGS transfer characteristics of our multilayer InSe FETs were measured with an Agilent B2901A parameter analyzer under ambient conditions. For the output characteristics (35 nm-InSe), the VDS is swept from 0 to 10 V while increasing VGS from −5 to 5 V in increments of 2 V (Fig. 2a). For the transfer characteristics (35 nm-InSe), the VGS is swept from −10 to 10 V at a VDS of 0.1 V (Fig. 2b). From the least-squares fit, we extract the linear electron mobility μ in the linear regime from InSe FETs with different thicknesses using the following equation: \(\mu = \left( {\frac{L}{{{\mathrm{WC}}_iV_{{\mathrm{DS}}}}}} \right)\left( {\frac{{{\mathrm{d}}I_{{\mathrm{DS}}}}}{{{\mathrm{d}}V_{{\mathrm{GS}}}}}} \right)\). The InSe FETs turned on at a negative gate bias, and the source/drain metal electrodes had ohmic contacts with the InSe channel layer, which enabled steady saturation currents. Characterization details for other structural devices are provided in the Supplementary Information (Supplementary Figs. 6, 7). However, more remarkably, PMMA/InSe/PMMA-HfO2 FETs have better electrical properties than those of typical InSe/SiO2 FETs or FETs with other structures. The small subthreshold slope (the following equation: \({\mathrm{SS}} = \left( {\frac{{d\log \left( {I_{\mathrm{D}}} \right)}}{{dV_{\mathrm{G}}}}} \right)^{ - 1}\)) of 260 mV/decade and highest ON/OFF current modulation of 107 extracted from the logarithmic plot indicate that the InSe transistor has a fast ON/OFF speed, which is an important factor for its electronic applications. A threshold voltage Vth = −2.5 V and effective electron mobility of 1200 cm2/V·s in the working regime were extracted from the linear plot of transfer characteristics (Fig. 2b). We experimentally investigated the impact of InSe FETs with different thicknesses. As shown in Fig. 2c, the carrier scattering exhibits an InSe thickness-dependent impact on the mobilities of layered InSe FETs, but our PMMA/InSe/PMMA-HfO2 FETs show much less thickness dependence, which will effectively contribute to device consistency in practical applications. The mobility increases as the InSe layer thickness increases from ~5 nm to 35 nm and then decreases as the channel thickness further increases for both SiO2/InSe and PMMA/InSe/PMMA-HfO2 FETs. Subsequently, InSe films with a thickness of ~35 nm were selected to build high-performance FETs.

Fig. 2
figure 2

Electrical characteristics and mobility of InSe FETs. a Output characteristics of a PMMA/InSe/PMMA-HfO2 FET. The channel length and width are 21 μm and 25 μm, respectively. b Transfer characteristics of PMMA/InSe/PMMA-HfO2 and InSe/SiO2 FETs at VDS = 0.1 V. c Thickness-dependent field-effect mobilities of multilayer InSe FETs with PMMA/InSe/PMMA-HfO2 and InSe/SiO2 configurations

Figure 3 shows the electrical stability behaviors in InSe transistors (35 nm-InSe). The most intuitive observation of electrical instability is the shift in the transfer curve during repeated transistor operations. During operation, the gate stress triggers interface defect states, which induce threshold voltage shifts. The PMMA/InSe/PMMA-HfO2 FETs feature a remarkable current reproducibility as the gate sweeps 10 times after a gate stress of VGS = ±10 V (Fig. 3a, b), which matches its negligible hysteresis shown in Supplementary Fig. 7. In addition, compared to the PMMA/InSe/PMMA-HfO2 FETs, the InSe/SiO2 FETs have a larger threshold voltage shift after gate stress (Fig. 3c, d). After the release of gate stress, the interface starts to return to its original state, and as a result, the transfer curve shifted back close to its curve sweep before the application of gate stress. The mobility of PMMA/InSe/PMMA-HfO2 is less sensitive to the gate bias stress than that of InSe/SiO2 and InSe/HfO2, as shown in Fig. 3e and Supplementary Fig. 8. Threshold voltages derived from the transfer plots show a maximum shift of ~0.6 V from the PMMA/InSe/PMMA-HfO2 FETs in Fig. 3f, which is less than 1/10 of that of the InSe/SiO2 FETs. More interface defects were triggered or induced with increased gate stress strength and time, which caused a larger threshold voltage shift (Fig. 3g, h). After 5 min, the threshold voltage shifts reach a steady state because most defect states participate in electrical activity in a short time, and few defects states become activated with stress strength and time. After over 30 days of storage at an ambient temperature, the threshold voltage shift in Fig. 3i remained at ~0.5 V under the same gate stress condition, and the threshold voltage shift of the transistor with the SiO2 dielectric was in the range of ~4–7 V. These results show that compared to other structural devices, our PMMA/InSe/PMMA-HfO2 FETs have superior electrical stability. In addition, InSe FETs with different encapsulation layers were fabricated to compare their effects on electrical properties and stability of the device. PMMA, Al2O3, HfO2 were used as FETs encapsulation layer, the electrical properties were systematically studied including mobility, current on/off ratio, hysteresis, and threshold voltage shift. PMMA encapsulated InSe FET had higher field-effect mobility, smaller hysteresis, and lower threshold voltage shift at the same test condition, and the results are shown in Supplementary Fig. 9 and Table S1.

Fig. 3
figure 3

Electrical stability of InSe FET. Transfer characteristics of a, b a PMMA/InSe/PMMA-HfO2 FET and c, d an InSe/SiO2 FET measured before the gate bias stress (prestress) and 10 consecutive IDSVGS curves immediately after a, c VGS = 10 V and b, d VGS = −10 V gate bias stress was applied for 300 s. e Field-effect mobility of the PMMA/InSe/PMMA-HfO2 FET and InSe/SiO2 FET for each measurement in the liner regime following the gate bias stress. f Threshold voltage shifts of the PMMA/InSe/PMMA-HfO2 FET and InSe/SiO2 FET for each measurement compared with the value of the pre-bias curves. g Threshold voltage shift with different gate stresses (−15, −10, −5, −1, 0, 1, 5, 10, 15 V) for 300 s. h Threshold voltage shift with different gate stress times (0, 10, 50, 100, 300, 500, 1000, and 2000 s) at gate stress VGS = ±10 V. i Threshold voltage shift of the PMMA/InSe/PMMA-HfO2 FET and InSe/SiO2 FET over 30 days

According to the electronic measurement shown above, spin-coating with PMMA clearly causes a significant improvement in device mobility, and the choice of different dielectric materials can also affect the device mobility. Screen of disorder may be an important reason according to previous study on dual layer PMMA to improve the mobility of 2D material.13,36 Furthermore, the improvement in mobility and stability of the transistor is key to nerve action signal detection. To further study the underlying physical mechanism of the device, first-principles calculations were performed using the Vienna Ab initio Simulation Package (VASP) code based on DFT.37,38 The band structure and electron effective mass of InSe on different dielectric materials (HfO2, Al2O3, SiO2) were studied. In addition, PMMA was placed on the InSe supercell to investigate the influence of PMMA. The calculation details are shown in the Methods section (shown in Supplementary Fig. 10). The band structures of intrinsic InSe, the InSe/SiO2 heterojunction and the InSe/PMMA heterojunction are shown in Fig. 4a–c, respectively. In general, the curvature of the band reflects the electron effective mass, and a lower effective mass usually indicates higher mobility. Clearly, the curvature of the InSe band decreases significantly after the formation of the heterojunction. Detailed calculation results are shown in Table 1. The increase in the electron effective mass was relatively small when InSe formed the heterogeneous junction with PMMA compared to other dielectric substrates, which was consistent with our hypothesis and experimental results. In addition, the introduction of PMMA did not cause obvious changes in the Fermi energy level, which means the Fermi Level of InSe in the InSe/PMMA structure is the same as that in pure InSe according to the calculation results. However, the Fermi Level of InSe in InSe/Al2O3, InSe/HfO2, and InSe/SiO2 structures changed according to DFT calculation results, which further indicated that PMMA has little influence on the electronic properties of InSe. In addition, PMMA is flexible and does not bring any lattice mismatch. The hydrophobic property of PMMA suppressed the chemical impurities of hydroxyl groups and absorbed water molecules at the oxidized dielectric (the water contact angles of PMMA and other dielectric materials are shown in Supplementary Fig. 4). These series of simulation results, together with the material characterization results for PMMA, provided a firm explanation for the previously observed experimental phenomena.

Fig. 4
figure 4

First-principles calculations for different interface conditions. The band structures corresponding to a intrinsic InSe, b InSe/SiO2, and c InSe/PMMA. d Schematic diagram of the InSe/PMMA structure

Table 1 DFT calculation of the relative effective masses for electrons under different conditions

Significantly, we summarize the electrical properties of 2D FETs from the literature obtained using different approaches in Table 2. Clearly, compared to the other 2D FETs, our PMMA/InSe/PMMA-HfO2 FETs show better electrical performance and stability, which further confirmed the advantage of our technology. Encouraged by the high performance of the InSe FETs, we applied them to sciatic nerve action potential recording (Fig. 5c). Before the actual recording of frog sciatic nerve action potential, we assessed the transistor response to weak electrical signals by applying a sequence of gate voltage VGS pulses with a peak value of 0.1–30 mV at intervals of 3 s and 1 s, recording the source/drain current IDS at VDS = 0.1 V (Fig. 5a, b). The IDS is linearly dependent on the input VGS defined by the formula \(I_{{\mathrm{DS}}} = \mu C_{{\mathrm{ox}}}\frac{W}{L}\left( {V_{{\mathrm{GS}}} - V_{\mathrm{T}}} \right)V_{{\mathrm{DS}}}\) in the linear regime with VT = −2.5 V. The correlation between the input VGS pulse and recorded IDS was experimentally derived and was consistent with the value theoretically calculated from the formula in linear regime (Supplementary Fig. 11). The sciatic nerve of a live frog was carefully dissected along the edge of the vertebral column and the sciatic groove located between the biceps femoris and semimembranosus muscle. During this entire process, the sciatic nerve was constantly dipped or soaked in Ringer’s solution to keep the nerve alive. For the recording of the biphasic action potential, the gate and source electrodes were connected to the middle part of the sciatic nerve, and the source-drain current IDS was recorded by a semiconductor parameter analyzer. The sciatic nerve was stimulated by intermittent clamping with tweezers, and its nerve action potential was applied to the gate electrode of the FET, which produced the corresponding source-drain current IDS (Fig. 5d). In order to avoid the stimulus artifact to interfere our recorded electrical signal, we used mechanical stimulation by tweezers clamping rather than stimulator. We found that by once clamping, one electrical signal appeared, which was accompanied by a single muscle twitch. Therefore, we think the signal recorded in our study definitely is compound action potential (CAP). Beside, as we know that typical sciatic nerve action potential is a characteristic biphasic potential. When both electrodes are placed on the surface of an axon, nerve is stimulated, and the nerve impulse produces a characteristic biphasic potential. The wave we recorded is as same as the typical one. (Mechanism diagram of sciatic nerve detection in Supplementary Fig. 12) Except nerve action potential, no gate bias was applied, since InSe transistor has threshold voltage of −2.5 V and turns on at VGS = 0 V. At VDS = 0.1 V, corresponding IDS produced by nerve action potential was recorded. Finally, the nerve action potential was derived from the recorded IDS according to the correlation shown in Supplementary Fig. 11. Compared to the conventional BL-420N measurement and direct measurement with the Agilent B2901A parameter analyzer, our InSe transistor recorded a much more distinct signal corresponding to the frog’s leg action (Fig. 5d and Video in Supplementary Fig. 13) because the transistors’ stable electrical performance. In addition, InSe FETs have great potential to be fabricated into flexible devices for in situ real-time recording. Supplementary Fig. 14 shows flexible PMMA/InSe/PMMA-HfO2 FETs on a polyimide substrate, even though more detailed work is needed to realize high-performance InSe FETs.

Table 2 Summary of 2D FETs in different reports
Fig. 5
figure 5

Sciatic nerve signal detection. a, b Drain-source current IDS with different gate voltage pulses (0.1, 1, 3, 5, 10, 20, 30 mV for 1 s and 3 s cycles). c Schematic diagram of structures with/without PMMA/InSe/PMMA-HfO2 FETs for detecting sciatic nerve signals. d Sciatic nerve signal detection with/without PMMA/InSe/PMMA-HfO2 FETs

In conclusion, a flexible/hydrophobic PMMA and high dielectric constant HfO2 dual-layer together with PMMA back-channel encapsulation allows InSe FETs to achieve both high field-effect mobility and electrical stability. The threshold voltage shift was maintained at 0.6 V after 30 days of storage under normal ambient conditions, while the field-effect mobility of the InSe FET was maintained at 1200 cm2/V·s. The PMMA layer used as a dielectric eliminated the lattice mismatch issue and did not cause obvious changes in the Fermi energy level of InSe. In addition, the hydrophobic property of PMMA suppressed the chemical impurities of hydroxyl groups and absorbed water molecules at the oxidized dielectric. The back-channel encapsulated PMMA protects InSe FETs from water and oxygen molecules influence at channel interface in the air. Highly stable InSe FETs with high mobility enabled real-time and in situ detection of sciatic nerve signals. This work revealed the important role of device electric stability in 2D materials, provides a valuable method to improve the electrical performance of 2D material-based FETs and may boost their practical applications, for instance, in the fields of neuron science, neurological diseases, and bio-molecules detection based diseases diagonosis.

Methods

Device fabrication

Highly doped p-type silicon substrate was cleaned by buffered oxide etching (BOE) solution. ALD of 30 nm HfO2 on the substrate was performed at 200 °C at a growth rate of 1.1 Å/cycle. The 250 nm PMMA (950 K) layer (4000 rpm for 2 min) was spin-coated onto the substrate with 30 nm HfO2 and then baked at 170 °C for 0.5 h in air. Layered InSe flakes were mechanically exfoliated from bulk InSe crystals and transferred to the prepared substrate using Scotch tape. To ensure clean contacts and avoid possible contamination from photolithography, the source and drain contacts, Ti/Au (10/50 nm), were defined by a shadow mask and deposited by electron-beam evaporation (2 Å/s). To prevent cracking of the metal, a copper sleeve was used during the evaporation process to shield from heat radiation. Finally, PMMA was spin-coated and baked to encapsulate the back-channel of the InSe FETs. Electrical characterization was carried out with an Agilent B2901A parameter analyzer under ambient conditions.

First-principles calculation

Before starting the calculations, the supercell of intrinsic InSe and a substrate with a lattice mismatch less than 4% was chosen (lattice mismatch is shown in Table 1). In addition, when considering the effect of PMMA, the supercell of intrinsic InSe was built first, and the PMMA molecules were placed on the supercell to form the heterostructure. The VASP code based on DFT was used to calculate the bandgap and effective masses of three material systems.37,38,39 The generalized gradient approximation (GGA) with the Perdew Burke Ernzerhof (PBE) function was used.39 Brillouin zone sampling was performed using a Monkhorst–Pack special k-point grid.40 The grids for the k-point sampling were 4 × 4 × 1 for the primitive cell. The force tolerance in structure relaxation was 0.005 eV/nm, the energy tolerance was 10−4 eV, and the energy cutoff was 400 eV.

Sciatic nerve signal detection

The frog was held on the left hand with cotton or cloth. The brain and spinal cord were destroyed by pitching. After pitching, the head, viscera, and skin were removed from the body. With the help of a glass dissecting needle, the sciatic nerve was carefully dissected along the edge of the vertebral column and the sciatic groove located between the biceps femoris and semimembranosus muscle. During this entire process, the sciatic nerve should be constantly dipped or soaked in Ringer’s solution, and it should not be touched by hand or with a metallic object. After stimulating the upper part of the sciatic nerve, the biphasic action potential and contraction of the gastrocnemius muscle were observed.