Over the last decade, the need for further miniaturization and increased functionality of electronic devices has triggered massive research in two-dimensional (2D) channel materials such as graphene and transition metal dichalcogenides (TMDs).1,2,3 Reliable electrical contacts between devices/materials and metal electrodes are crucial, as the contact resistance can strongly influence or dominate the behavior of the entire device. Depending on the contact status at the metal–channel junction, Ohmic or Schottky, the flow of charge carriers across the device can be decisively deteriorated.4 Thus, the reliable formation of contacts to each new channel material proves challenging and has to be investigated in detail.

Graphene has been considered one of the most promising candidates for future nanoelectronics due to its unique electrical properties.5 Contact resistivity in graphene devices has been widely studied and a wide range of contact resistances (~102 to ~103 Ω µm) has been reported, depending on the contact metal, surface states, and contact geometry.6,7,8,9 Following the impressive advances in graphene, various layered 2D TMDs have been tested in a wide range of device applications, including field-effect transistors (FETs),10,11 photodetectors,12,13,14 and sensors.15,16 Up to now, molybdenum and/or tungsten-based materials have been the main focus of 2D TMD research, and the majority of studies on electrical contacts to 2D TMDs have concentrated on these materials.17,18,19 However, compared to classical silicon-based devices, these TMDs still show relatively inferior performance and less environmental stability in device applications.20,21,22,23 Moreover, the high growth temperature (>600 °C) associated with TMD synthesis by chemical vapor deposition (CVD), which is typically used for large-scale TMD film synthesis,24,25,26 can limit their compatibility with current semiconductor processing.

On the other hand, there are other relatively unexplored members of the TMD family such as group-10 TMDs. Recently, the electronic structure and properties of these materials have been theoretically evaluated and, as a consequence of their promising characteristics, they have been proposed for use in electronic device applications.27,28 Platinum diselenide (PtSe2) is one such group-10 TMD which is known to be a semimetal in bulk form with zero bandgap.29 Theoretical calculations suggested a transition from semimetal to semiconductor with reduced PtSe2 thickness27,30 and it was shown experimentally by Wang et al. that monolayer PtSe2 has a bandgap of ~1.2 eV.31 In addition, we recently reported that layered PtSe2 can be synthesized in a scalable manner at low temperature (400 °C) by thermally assisted conversion (TAC) of pre-deposited Pt layers and utilized as the active material in optoelectronic and gas-sensor devices.32,33 Such low-temperature synthesis may potentially have a high impact on practical device applications since it allows integration of PtSe2 with standard semiconductor back-end-of-line processing.34,35,36 In this regard, it is critical to evaluate electrical properties and contacts to PtSe2 in electronic devices.

Here, PtSe2 channels with controlled dimensions and thicknesses were grown using a TAC method. Electron beam lithography (EBL) was used to fabricate transmission line method (TLM) structures to extract contact resistivity and sheet resistance of the PtSe2 devices. In addition, electrical characterization of PtSe2 FETs was conducted to study the charge-transport characteristics of the PtSe2 devices. Finally, we investigated the effect of “edge” or side contacts on the contact resistivity using well-defined hole patterns in the contact region of the PtSe2 channel.

Results and discussion

PtSe2 device channels were synthesized by direct selenization of pre-deposited Pt layers with different thicknesses. As reported in our previous studies,32,33 the PtSe2 synthesized by a TAC process has a polycrystalline structure, which is also observed in scanning electron microscopy (SEM) images (Fig. S1 of the Supplementary Information) of the PtSe2 film surface. According to atomic-force microscopy (AFM) measurements of the thicknesses of Pt layers before and after selenization, it has been found that the initial Pt thickness expands approximately four times after selenization. Details of the AFM characterization are presented in Figs. S2 and S3 of the Supplementary Information. Previous studies on TAC growth of TMDs have shown that the orientation of the resultant films depends on the starting metal thickness with thicker metal films leading to horizontal growth, perpendicular to the growth substrate.37 A recent study on the electrocatalytic properties of PtSe2 indicated that this holds true for TAC growth of PtSe2, with significant contributions from perpendicular growth seen for PtSe2 thicknesses >20 nm.38 This is consistent with our observations, our PtSe2 films looked “cloudy” if thick (>5 nm) Pt films were used and so for the purpose of this study only Pt films with thickness of 5 nm or less were used. In this thickness regime we expect the growth to be mostly vertical, or parallel to the growth substrate. A schematic diagram of the film growth process is presented in Fig. 1a. First, the channel area was defined on the substrates by EBL. After Pt deposition and lift-off, the Pt samples were selenized via a TAC method. Raman spectra of the PtSe2 layers grown from various Pt thicknesses (0.5, 2, and 5 nm) are shown in Fig. 1b. Two prominent peaks at ~177 cm−1 and ~210 cm−1 can be seen in the spectra. They represent the typical Raman fingerprint of layered PtSe2 with a 1T type crystal structure and are related to the Eg (~177 cm−1) and A1g (~210 cm−1) Raman active modes, respectively.32 The Eg mode indicates an in-plane vibrational mode of Se atoms and the A1g mode is an out-of-plane vibration of Se atoms. As the films get thicker, a slight red shift of the Eg mode is observed, alongside an increase in the relative intensity of the A1g mode, consistent with previous reports.32,33 Such an increase in the relative intensity of the A1g mode implies a greater out-of-plane contribution, which may be due to enhanced van der Waals interactions in the thicker films. Additionally, we investigated the sulfurization of Pt films using a S source in place of Se. Interestingly, our preliminary studies suggest the formation of PtS rather than PtS2 as detailed in Fig. S4 of the Supplementary Information.

Fig. 1
figure 1

Device fabrication and characterization. a Schematic diagram of the PtSe2 channel synthesis process using a TAC method. b Raman spectra of PtSe2 films of different Pt deposition thickness normalized to the Eg mode intensity. Initial Pt deposition thicknesses are 0.5, 2, and 5 nm. c SEM image of the fabricated PtSe2 channel device with a TLM structure (left, scale bar 50 μm) and its enlarged image (right, scale bar 5 μm). The contact spacing increases from 1 to 9 µm with a step of 1 µm

TLM measurements were used at room temperature to determine the contact resistance of the PtSe2 devices in this work.39 TLM structures were patterned on the substrates with predefined PtSe2 channels by EBL. The contact spacing was varied from 1 to 9 µm in 1 µm steps. SEM images of a TLM structure on a PtSe2 channel are shown in Fig. 1c. Two representative metals with low and high work functions, Ti and Ni, were chosen and used to contact the PtSe2 channels, both of which were selenized from 5 nm thick initial Pt layers. The contact resistances of these were compared through dc current–voltage (I–V) measurements of the TLM structures. Figure 2a and b shows I–V data measured from Ti and Ni-contacted PtSe2 TLM structures with a channel width of 3 µm, respectively. The linear I–V curves indicate that both Ti and Ni electrodes form good ohmic contacts with PtSe2 channels. Values of the contact resistance for each metal and the sheet resistance of the PtSe2 channel can be extracted by extrapolation from linear fits of the plots of the total resistance (RT) vs. the contact spacing (Fig. 2c, d), wherein the y-intercept and the slope of the fits provide information on the contact resistance and sheet resistance. Figure 2e shows contact resistivity values of each metal for different PtSe2 channel widths, where the contact resistance values were normalized to channel width for direct comparison. It was found that the Ti-contacted device had a contact resistivity more than one order of magnitude higher than the Ni-contacted device. Considering the work function values of the contact metals (Ti: 4.3 eV, Ni: 5.2 eV), we observe that the metal with a higher work function has a lower contact resistance with PtSe2. The sheet resistance values of the PtSe2 channels in Fig. 2f are quite similar to each other (500–600 Ω/□) for both contact metals, which can be expected from the identical PtSe2 channel thicknesses for both devices.

Fig. 2
figure 2

Electrical characterization of PtSe2 TLM devices. I–V plots of the TLM structure with various PtSe2 channel length values (L) for a Ti/Au and b Ni/Au-contacted devices, and the associated plots of the total resistance (RT) vs. PtSe2 channel length for the c Ti/Au and d Ni/Au-contacted devices. The initial Pt deposition thickness and the channel width of the devices are 5 and 3 µm, respectively. e Contact resistivity and f sheet resistance values extracted from the TLM measurements for the Ti/Au and Ni/Au-contacted devices with different PtSe2 channel width values

Ni-contacted TLM structures were then fabricated on PtSe2 channels with different thicknesses, which were selenized from 0.5, 2, and 5 nm thick initial Pt layers. The Ni–PtSe2 contact resistivity and sheet resistance were extracted by analyzing the TLM measurement data, RT vs. contact spacing, in Fig. 3a and b. The extracted values of the contact resistivity and sheet resistance are plotted against the film thickness in Fig. 3c and d. When the same Ni electrodes were deposited on the PtSe2 channels with various thicknesses, devices with thinner PtSe2 channels show much higher contact resistivity and larger sheet resistance. This can be attributed to the nature of layered PtSe2, whereby the electronic character changes from semimetallic to semiconducting as the number of layers decreases.27,30,31 The thinner PtSe2 can be expected to be more semiconducting than the thicker, resulting in higher contact resistivity with metal electrodes as well as larger sheet resistance. The semiconducting characteristics of the thinner PtSe2 are also supported by the results of electrical measurements at low temperatures. The I–V plots of a PtSe2 film, derived from a 0.5 nm thick Pt layer and measured in a temperature range of 78–340 Kelvin (K), reveal clear temperature dependence. As the temperature is reduced there is a consistent rise in resistance, indicating the semiconducting nature of the PtSe2. Details of the temperature-dependence measurements are presented in Fig. S5 of the Supplementary Information.

Fig. 3
figure 3

Investigation of the effect of PtSe2 thickness on device performance. Plots of the total resistance (RT) vs. PtSe2 channel length for the Ni-contacted TLM structures with different PtSe2 thicknesses, synthesized from the a 2 nm and b 0.5 nm thick Pt layers with 1 µm of channel width. Summary of c contact resistivity and d sheet resistance values extracted using TLM method for the different PtSe2 thicknesses

Charge-transport measurements of PtSe2 FETs were carried out at room temperature in ambient conditions to further investigate the electrical properties of PtSe2 films with different thicknesses. PtSe2 channels with a length of 5 µm and a width of 1 µm were probed via two separate metal source and drain electrodes, with gate biases applied to the silicon substrate in a back-gate configuration. The output characteristics of the FETs with PtSe2 channels synthesized from 5, 2, and 0.5 nm thick initial Pt layers are plotted in Fig. 4a–c, respectively. For all devices, the drain–source current (Ids) increases linearly with the applied dc drain–source voltage (Vds), implying good ohmic contact of the Ni electrodes with the PtSe2 channels. As expected, the device with a thicker PtSe2 layer shows higher conductivity. The gating characteristics of the FETs were examined under a dc back-gate bias (Vgs) in the range of −80 to +80 volts (V). While the FETs with PtSe2 channels synthesized from the 5 and 2 nm thick Pt layers show hardly any gate dependence, the PtSe2 FET from the 0.5 nm thick initial Pt layer shows a clear gate dependence with p-type conduction. This is consistent with the previous results that contact formation with a high work function metal reduces the contact resistance at the metal-PtSe2 junction. Also, this data supports the hypothesis that PtSe2 becomes more semiconducting as it gets thinner. The field-effect mobility (μ) was extracted from the transfer characteristics of the PtSe2 FETs selenized from the 0.5 nm thick Pt layer in Fig. 4d, using the expression μ = [L/(W × Cox × Vds)] × [∂Ids/∂Vgs], where L is the channel length, W is the channel width, Cox is the capacitance of the insulating layer between the gate and the channel. The mobility was estimated to be a maximum of 0.6 cm2 V−1 s−1, which is lower than previously reported values (7–210 cm2 V−1 s−1) obtained from high-temperature CVD-grown single crystalline, or mechanically exfoliated PtSe2.40,41 However, considering the benefits of our growth process, namely, the low synthesis temperature, scalability and ease of controlling layer thickness, this is quite striking. Such a relatively low mobility likely originates from the polycrystalline structure, with randomly distributed PtSe2 grains, observed for TAC-grown PtSe2.32,33 This polycrystallinity, and associated thickness variation over large areas, is also the most likely cause of the relatively poor gate control seen in our gate-response curves. Additional efforts to optimize the synthesis process, through the use of epitaxially deposited Pt or highly crystalline substrates, and the realization of local top-gates with high-k dielectrics, are expected to improve the mobility. Furthermore, better control over the Pt deposition conditions, and the use of post-growth treatments such as annealing, can be expected to improve the film uniformity leading to better gate control. In order to assess the stability of PtSe2 channels, we repeated I–V measurements on the same device (PtSe2 channel with a length of 5 µm and a width of 1 µm) in ambient conditions with an interval of 20 days and monitored the variation of RT of the device for 40 days. As presented in Fig. S6 of the Supplementary Information, the measured RT was 8.1 MΩ from the first measurements, 8.3 MΩ from the second measurements after 20 days, and 9.4 MΩ from the last measurements after 40 days. This indicates that the PtSe2 channel is quite stable with a resistance increase of 15% of the initial value after 40 days without any passivation or post-treatment.

Fig. 4
figure 4

Gate-dependent electrical measurements of PtSe2 devices. Output characteristics (Ids vs. Vds) of PtSe2 FET devices with PtSe2 channels selenized from a 5 nm, b 2 nm, and c 0.5 nm thick Pt layers under various back-side gate biases (Vgs) from −80 to 80 V. d Transfer characteristics (Ids vs. Vgs at Vds = 1 V) of the PtSe2 FET device with a PtSe2 channel selenized from a 0.5 nm thick Pt layer

Lastly, we investigated the effect of “edge contacts” on the contact resistance of PtSe2 TLM structures. There have been continuous efforts to achieve low contact resistance in 2D-material-based devices, including local plasma or ultraviolet/ozone treatment of the contact area42,43 and molecular doping of the channel materials.44 However, these methods require additional processes and can cause damage to the channel materials. Forming an “end-contacted” interface between metal and graphene was proposed as another way to reduce contact resistance,45 wherein the end-contacted structure at the graphene–metal contacts facilitates chemical bonding between the graphene and the contact metal, enhancing the carrier injection at the contact area. Such an approach has previously been experimentally adopted for graphene-based devices, resulting in a significant improvement in the contact resistance.46,47,48 Based on this principle, we expect that the edge-contacted structure shown here improves the carrier injection at the metal–PtSe2 interface. Arrays of holes with a hole size of 200 × 200 nm were included on the contact area of the Pt channel design for EBL, generating channel patterns with empty holes on the contact areas by EBL, as presented in Fig. 5a and b. As the PtSe2 is aligned parallel to the growth substrate these holes leave many edges exposed. The contact metal fills in these holes leading to the formation of edge contacts between the PtSe2 channel and metal electrodes and increasing the total area of exposed channel edges at the contact region in the TLM structures. The PtSe2 channels of all the devices were selenized from 0.5 nm thick Pt layers with a width of 2 µm, and three different types of hole array patterns (side 1-line, side 2-line, and center 2-line) were fabricated with Ni electrodes. The contact resistivity of the normal PtSe2 TLM device without holes and the device with holes at the contact region were extracted and are compared in Fig. 5c. While there is no clear dependence of the contact resistivity on the number and location of hole arrays at the contact region, distributed between 2 × 105 and 6 × 105 Ω µm, all the devices with the hole patterns at the contact region exhibit 50–70% lower contact resistivity than the conventional device. In contrast, no significant difference in the sheet resistance was observed for all the PtSe2 channel devices in Fig. 5d, indicating that the quality of the PtSe2 channels is nearly constant for all devices.

Fig. 5
figure 5

Edge contacting of PtSe2 TLM structures. a Schematic diagram of the metal (Ni)–PtSe2 contact area with/without holes on the PtSe2 channel. b SEM image of the PtSe2 channel with 2-line holes at the side of the metal contact area before metal electrode deposition (scale bar, 1 μm). Extracted c contact resistivity and d sheet resistance values from the PtSe2 TLM structures (0.5 nm of starting Pt thickness, 2 µm of channel width) with and without holes on the PtSe2 channel at the metal-PtSe2 contact area

In summary, we have investigated the electrical contact properties of PtSe2 channels by the TLM method. Initial Pt layers with thicknesses of 0.5, 2, and 5 nm were selenized at low temperature using a TAC method, realizing robust PtSe2 layers with different thicknesses. When comparing the contact resistivity values of the PtSe2 TLM devices with two different contact metals, Ti and Ni, it was found that Ni forms a better electrical contact to the PtSe2 channel. We also observed that the thinner PtSe2 films have a higher contact resistivity and larger sheet resistance from the TLM measurements, implying that thinner PtSe2 films become more semiconducting. In addition, the charge transport characteristics of PtSe2 FETs were investigated. Only the device derived from the thinnest PtSe2 layer (0.5 nm) showed a clear gate dependence with p-type conduction, which confirms the transition of PtSe2 from semimetal to semiconductor with decreasing thickness. Furthermore, the effect of edge-contacted structures on the contact resistance was examined. Arrays of holes were patterned in PtSe2 to increase the “edge-contacted” area of the layered PtSe2 film at the metal interface. We found that the edge-contacted structures reduce the contact resistivity, which we attribute to enhancement of the carrier injection at the contacts. Though more comprehensive studies should be carried out in the future to fully understand the fundamentals of the electrical contact properties, our findings provide a quick insight into the realization of high-performance nanoelectronic devices based on layered PtSe2.


P-type silicon wafers (boron, 3 × 1015 cm−3, <100>) with a thermally grown silicon dioxide (SiO2, thickness: 290 nm) layer were prepared as substrates for the devices. An EBL system (Raith EBPG-5000Plus) was used to pattern the PtSe2 channels and contacts. Initial Pt layers with different thicknesses were sputtered onto the substrates using a Gatan coating system (Gatan 682 PECS) with a deposition rate of <0.1 nm per second, followed by a lift-off process.

A TAC process was used to synthesize layered PtSe2 thin films, as described in our previous work.32,33 The sputtered Pt samples and the Se source (Sigma-Aldrich) were placed in two separate, independently controlled heating zones of a quartz tube furnace. The primary heating zone where the Pt samples were located was heated to 400 °C and the second heating zone for the Se source was heated to the melting point of Se (~220 °C) under Ar/H2 (9:1) gas flow, leading to the formation of layered PtSe2 thin films. Different metal electrodes of titanium/gold (Ti/Au, 20/150 nm) and nickel/gold (Ni/Au, 20/150 nm) were deposited to form TLM structures using an electron beam evaporation system (Plassys) without doing any additional process before evaporation, followed by a lift-off process.

Edge-contacted structures between the channel and metal electrodes were realized by including arrays of holes (a hole size of 200 × 200 nm) in the contact area of the channel design for EBL. The channel patterns, with hole arrays on the contact area, were generated by EBL, resulting in a contact area with empty holes on the channel after Pt deposition. These holes remain in the channel area post selenization. The metal electrodes were patterned by EBL after the selenization of the Pt. The contact metal was evaporated on to the contact region of the PtSe2 channel with holes, without doing any additional processing at the contact area before evaporation. Further information on the formation of the edge contacts is given in Fig. S7 of the Supplementary Information.

Raman spectra were recorded with a Witec Alpha 300R confocal Raman microscope, using an excitation wavelength of 532 nm and a spectral grating with 1800 lines/mm. SEM images were taken using a JEOL SEM (JSM-IT300) at a high-vacuum mode with an accelerating voltage of 2 kV. Electrical measurements were performed at room temperature under ambient conditions using a Karl Süss probe station connected to a Keithley semiconductor analyzer (SCS4200).

Data availability

The data sets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.