Reversible hysteresis inversion in MoS2 field effect transistors

The origin of threshold voltage instability with gate voltage in MoS2 transistors is poorly understood but critical for device reliability and performance. Reversibility of the temperature dependence of hysteresis and its inversion with temperature in MoS2 transistors has not been demonstrated. In this work, we delineate two independent mechanisms responsible for thermally assisted hysteresis inversion in gate transfer characteristics of contact resistance-independent multilayer MoS2 transistors. Variable temperature hysteresis measurements were performed on gated four-terminal van der Pauw and two-terminal devices of MoS2 on SiO2. Additional hysteresis measurements on suspended (~100 nm air gap between MoS2 and SiO2) transistors and under different ambient conditions (vacuum/nitrogen) were used to further isolate the mechanisms. Clockwise hysteresis at room temperature (300 K) that decreases with increasing temperature is shown to result from intrinsic defects/traps in MoS2. At higher temperatures a second, independent mechanism of charge trapping and de-trapping between the oxide and p+ Si gate leads to hysteresis collapse at ~350 K and anti-clockwise hysteresis (inversion) for temperatures >350 K. The intrinsic-oxide trap model has been corroborated through device simulations. Further, pulsed current–voltage (I–V) measurements were carried out to extract the trap time constants at different temperatures. Non-volatile memory and temperature sensor applications exploiting temperature dependent hysteresis inversion and its reversibility in MoS2 transistors have also been demonstrated. Defects and traps in MoS2 van der Pauw devices give rise to a hysteresis inversion mechanism which is reversible with temperature. A team led by Saurabh Lodha at the Indian Institute of Technology Bombay performed variable temperature hysteresis measurements on four- and two-terminal MoS2 devices, both suspended and supported on a SiO2 substrate. The onset of a clockwise hysteresis at room temperature was attributed to intrinsic MoS2 defects, whereas an additional mechanism resulting in an anticlockwise hysteresis was observed at higher temperature, and attributed to extrinsic charge trapping and de-trapping between the oxide and the silicon gate. By leveraging the temperature dependence of the hysteresis in MoS2, the authors developed a non-volatile memory and a temperature sensor.

of the main manuscript, change in R A /R C with gate voltage results from different current paths in different measurement configurations, as a particular defect depending on its location will affect one configuration more than the other. To validate the van der Pauw measurements, we also characterized reciprocity i.e. the ratio of R C /(R A + R B ), and found it to be equal to 1 as expected and shown in Figure S1b

EFFECT OF GATE VOLTAGE RANGE ON CROSSOVER TEMPERATURE
Hysteresis crossover (∆V T H ∼ 0) at 350 K occurs due to movement of the threshold voltages in forward (FS) and reverse (RS) sweeps towards each other. The crossover temperature at which ∆V T H =0 is seen to be a function of the maximum gate voltage (V max GS ) as shown in Figure S2. Hysteresis collapse occurred at higher temperature of 425 K for smaller V max GS (V GS range of −40 to 80 V) as compared to 350 K for V max GS of 100 V (V GS range of ± 100 V). shown in Figure S5a. This lack of a V GS shift in g m peak indicates that the degradation in g m is likely due to intrinsic defects/traps till nearly 350 K. However, a further increase in temperature enables the oxide trap mechanism (charge exchange between gate and oxide).

COMPARISON OF HYSTERESIS IN SUPPORTED AND SUSPENDED
As a result, negative charges in the oxide (i.e. due to electron tunneling from p + Si gate) shift the g m peak towards right (higher V GS ) in the forward sweep as shown in Figure S5a.
There is no shift in the g m peak for the reverse sweep characteristics shown in Figure S5b

DEVICE STRUCTURE USED IN SIMULATIONS
The proposed intrinsic and oxide trap models used to explain hysteresis phenomena such as hysteresis crossover and inversion were validated using simulations. Figure S7

APPLICATION: MEMORY AND TEMPERATURE SENSOR
We demonstrate two possible applications using thermally assisted hysteresis inversion in MoS 2 . Firstly, the hysteresis transfer curve shown in Figure S9a can be exploited for non-volatile memory applications. Figure S9b shows a device working as a memory at 375 K. As the hysteresis is due to charge trapping/detrapping that requires significant change in temperature or bias to change, it is possible to have steady-state charged or discharged states for the intrinsic traps in MoS 2 or oxide traps in SiO 2 which can be used as '0' and '1' states of a memory device. The voltage waveform depicting read and write actions for both '0' and '1' states along with the corresponding conductance waveform are shown in Figure   S9b. Reset and write voltages are chosen to be far apart and there is a large distinction in the low conductance read '0' and high conductance read '1' states.
This device can also be used as a temperature sensor. Figure S9c shows ∆σ S for varying V GS at different temperatures that has been mapped to the operating temperature at Figure S9d. Note that ∆σ at 350 K increases for V GS > 0 V due to transfer of trapped oxide charges back to the gate. Similar trend is also shown in Figure 2c of the main manuscript, where σ F S increases and crosses σ RS for V GS > 0 V. However at higher temperatures (i.e. 375 K and 400 K) σ F S increases but does not cross σ RS due to a large difference between them. Further, hysteresis inversion facilitates a larger working temperature range for these devices compared to previous reports where hysteresis collapses after a particular temperature.
Thermally assisted memory has been demonstrated using anti-clockwise hysteresis at 375 K in the main manuscript. Here we show how hysteresis inversion can be exploited to realize a reduction in read power dissipation for heavy-'0' and heavy-'1' storage applications. Heavy-'0'/'1' refers to applications where the occurrence of one state is more frequent than the other. Depending on the operating conditions (heavy-'0' or heavy-'1'), one can assign an operating temperature for the device which has lower read conductance for the most occurring state ('0' or '1'). For example, in case of the devices presented in this work, heavy-'0' and heavy-'1' conditions can be operated at 375 K and 300 K respectively as shown in Figure S10 to achieve low read power dissipation. 9 FIG. S10. Thermally assisted reconfigurable memory operation using reversible hysteresis inversion.
The σ s − V GS characteristics at (a) 300 K and (b) 375 K used to implement the memory function shown in (c,d). (c,d) The upper plot shows the gate voltage sequence applied to the device while the lower one shows the resulting variation of the sheet conductance measured in response to this sequence for 300 K and 375 K respectively.