A novel semi-quadratic buck-boost structures with continuous input current for PV application

This paper recommends new design for non-isolated semi-quadratic buck/boost converter with two similar structure that includes the following features: (a) the continuous input current has made it reasonable for PV solar applications and reduced the value of the capacitors in the input filter reducing the input ripple as well as EMI problems; (b) the topology is simple, and consists of a few numbers of components; (c) the semiconductor-based components have lower current/voltage stresses in comparison with the recently recommended designs; (d) semi-quadratic voltage gain is D (2 − D) / (1 − D)2; (e) 94.6 percent from the theoretical relations and 91.8 percent from the experimental for the output power of 72W, the duty of 54.2 percent, and output voltage of 72 V are the efficiency values in boost mode; (f) 89.3 percent from the theoretical relations and 87.2 percent from the experimental for the output power of 15W, the duty of 25.8 percent, and output voltage of 15 V are the efficiency values in buck mode. One structure is the continuous output current and negative output polarity, and other structure is positive output polarity. The recommended topologies have been studied in both ideal and non-ideal modes. The continuous current mode (CCM) is the suggested mode for the proposed converters. Moreover, the requirements of CCM have been discussed. The various kinds of comparisons have been held for voltage gain, efficiency, and structural details, and the advantages of the suggested design have been presented. A small-signal analysis has been completed, and the suitable compensator has been planned. Finally, PLECS simulation results have been associated with the design considerations.

Many buck/boost DC converters were studied in the literature devoted to traditional DC converters, such as buck-boost, ZETA, SEPIC, CUK, buck and, boost converters 12,13 .Solar Power Optimizers (SPOs) and other applications requiring higher voltage gain can benefit from these converters [14][15][16] .Figure 1 represents the applications of PV solar systems with SPOs.It is evident that solar energy power can be delivered to the grid using a step-up/ down converter with higher voltage gain.In situations where there is no grid connection (for instance, because the grid is redundant), it may be utilized as a buck/boost converter in uninterruptible power supply (UPS) systems for charging the lower voltage battery.As a non-isolated converter topology has no isolation among the output and input sides, the converters' output side can be directly affected by the changes on the input side.They have a lower component count than the isolated converter topology 17 .Though there are some small issues with them, which should be stated, they include poor voltage gain, higher duty cycle ratios, as well as additional circuitry for optimum performance.An analysis of some topologies mathematically has been done in order to gain a full understanding of the dynamic behavior of the converter 18 .For RE applications, SEPIC converters were utilized with various elements 19 for lessening the voltage stress on the main switch and increasing the voltage gain.A novel buck/boost DC/DC converter was moreover given with two MOSFETs requiring two drivers.This increases the complexity of the control system along with the discontinuous inputs and outputs 20 .With a discontinuous input current port and an extreme duty cycle, this converter is twice as big as the fundamental buck/boost converter.Hence, it is not usable due to the limitations of power semiconductor tools 21 .
In 22 , proposed semi-quadratic DC converters with many elements and continuous input current port.A novel coupled-inductor buck-boost converter was presented 23 , which consists of a simple configuration with two cascade semi-stages.There are several properties of this configuration, including common ground, continuous input current and ultra-extended output voltage.The output current is discontinuous despite its enhanced performance in both boosting and bucking modes.The converter requires two floating switches.Some introduced quadratic buck/boost converters 24,25 , with continuous input current port and lower voltage gain.A novel (N/O) buck/boost converter was proposed by combining buck-boost and conventional boost converters 26 .However, there is an excessive amount of stress across one switch due to the negative and discontinuous output voltages.A boost mode and a buck/boost mode with a high gain ratio are two operating modes.Towards this end, several boosting approaches, such as the employment of voltage multipliers, switched inductors, magnetic coupling switched capacitors, and multistage techniques, are covered in 27 .Using dual working modes, a DC/DC converter with positive output displayed reduced total switching device power 28 .There were two modes of operation: step-up and step-up/down.
A N/O converter was presented with a wide conversion ratio in 29 , which suffers from sporadic input/output current.There is a critical role for N/O polarity in several industries, including the transmission of data, solar, and wind power generation.However, the discontinuous input current of the converter may have limited usage in most applications, like solar energy conversion.A prolonged multi-cell buck-boost converter was proposed based on the conventional SEPIC converter 30 , which requires several components but possesses limited voltage gain.A higher step-up buck-boost converter was also suggested 31 , which has a main switch and reduced stress around the main switch.Though, the three diodes of the converter possess high voltage stresses.A non-quadratic single switch having continuous input/output current ports was presented with no common ground connecting the input and output 32 .ZETA DC converters also exist 33 .The ZETA converter has a voltage gain twice that of the conventional ZETA converter.The design of a transformerless DC/DC converter with dual operation modes buck/boost is presented.This system acts as a common ground, continuous input current between the input and output terminals since it have a common and simple configuration 34 .Moreover, dual-mode transformerless inverters were also prototyped and presented 35 .Using this simple structure, the single-phase inverter overcomes the shortcomings of modern dual-mode inverters by providing various voltage gain ratios.There is a low voltage www.nature.com/scientificreports/gain ratio in this converter.The continuous current in the output and input positive terminal polarity and the output polarities of a quadratic DC/DC converter were compared and evaluated 36 .In addition, an innovative transformerless converter with a quadratic buck-boost design has been proposed with positive output 37 .Due to the presence of inductive filters in the input and output ports, the structure has continuous input and output currents.In order to solve the discontinuity problem, a quadratic buck-boost converter was developed with a low number of elements and continuous inputs and outputs 38 .A similar study introduced an output and input inductive filter buck-boost converter 39 .The switch used in this converter has a lower voltage stress.However, this converter includes a greater number of semiconductor elements than the other structures.The ripple of the output voltage of the quadratic gain converter 40 at the selected operating point is zero.However, high voltage stress across the output diode, this converter transmits negative voltage to output.The converter's quadratic output voltage gain 41 , in comparison to traditional buck-boost converters, allows it to achieve improved buck or boost capabilities when the duty cycle is either higher or lower than 50 percent.This converter has advanced features including input and output current ports that provide a smooth flow of electricity, reducing the fluctuations in both the input and output.As a result, it is a suitable option for applications in RE.Three different quadratic buck DC-DC converter schemes were presented, each with the ability to flip to a semi-quadratic buck-boost configuration.The topology introduced earlier in 42 provides a cascaded structure where two similar boost converters are connected back-to-back to increase the output voltage.However, the numerous components in this design increase the size and cost.The proposed converter 43 is described in detail.It presents a novel high-voltage gain converter that utilizes the asymmetric input voltage of inductors.This converter offers high power density, desirable output, and constant input, making it suitable for renewable energy applications.Additionally, cascaded boost converters 44 with quadratic gain characteristics are proposed, where component count is minimized and voltage stress on passive devices is reduced.However, the voltage gain remains lower in one such model compared to another.Furthermore, both models require separate control grounds for semiconductor switches, necessitating two control power supplies.A non-isolated quadratic boost DC converter is introduced 45 , which provides high output voltage gain with a lower number of components.An input filter design makes the converter suitable for photovoltaic applications.Notably, this converter utilizes a single switch ground, eliminating the need for an additional control power supply.In a converter described in 46 , the power switch experiences a high voltage equal to the output voltage, which distributes the voltage stress across two power switches and lowers the voltage stress on the switches.Numerous studies have proposed improved architectures for quadratic boost converters due to their flexibility for new combinations, continuous input current, the presence of ground between the source and load, and clear voltage gain for the foundation of new configurations.A topological structure is established to ensure a secure transition from a particular switch to a different one, while preserving the functional contribution of all other components towards achieving efficient power conversion, as documented in 47 .A non-isolated DC buck boost converter with low element count and low electrical stress on the elements is presented 48 .But the voltage gain ratio of this converter is very low.The Cuk converter is the only common converter achieving continuous outputs and inputs current with a lower number of components (one switch, one capacitor, one diode, and two inductors) and flexible output.However, it has output voltage inversion.Due to its step-up/step-down capability, the Cuk converter is extensively utilized in power electronic applications.As long as the continuous output current is taken into account, parallel connections of the converter output can be made to a voltage source with negligible shunt capacitance.Utilizing larger inductors and a higher switching frequency can minimize the input current ripple problem.However, bulky filters are required by these conventional solutions; thus, they are expensive and require larger sizes along with higher switching losses.Consequently, the proposed method utilizes minimal filtering to provide a low-input current ripple converter.In this paper, two converters are proposed for PV sources to reduce input current ripple, thereby maximizing overall efficiency (while avoiding coupling an inductor).Moreover, one of semi-quadratic buck/boost converters are presented that overcomes the deficiencies of a conventional Cuk converter.It has extensive conversion ratios, as well as a continuous input/output current port.Therefore, it is appreciate for requests involving RE.
The suggested paper is organized as below.The semi-quadratic buck-boost structures and its operation, efficiency analysis and power loss analysis are described in Sect."Proposed structuers, operation principles, and steady-state evaluation".Section "Analysis and design parameters" analysis and design of parameters inductor and capacitor.In Sect."Small signal modeling", small signal modeling is evaluated.Section "Comparison with existing converters" deals with the benefits of the proposed converter in comparison with existing converters.The PLECS simulation and experimental results are shown in Sect."Experimental result and building a prototype".Furthermore, Sect."Building a prototype and performance evaluation" shows the investigational outcomes of the proposed structures prototype.Finally, Sect."Conclusion" concludes the paper with the main findings.

Proposed structuers, operation principles, and steady-state evaluation Proposed semi-quadratic buck-boost converters
The most important characteristics of a DC buck/boost converter utilized by solar PV systems are constant input/ output current port, cost-effectiveness, high efficiency and low noise.
Figure 2 shows the developed two similar semi-quadratic buck/boost converters.Three capacitors (C 1 , C 2 , C o ) and three inductors (L 1 , L 2 , L 3 ) and, two switches (S 1 , S 2 ), two diodes (D 1 , D 2 ), and a resistive load (R o ) are combined to attain the high-voltage gain buck/boost converter.
By considering the ideal components and then taking all capacitors with the appropriate size to keep nearly constant voltages, the steady-state analysis for the converter can be simplified.As a result, the voltage and current were assumed to be constant for the duration of a full period.In addition, Fig. 3 includes some graphs pertaining to converters, such as diode voltages, switch voltages, inductor currents, etc.

States of operation principles
It is necessary to take into consideration both steady-state conditions as well as CCM when calculating the characteristics of the proposed converters.Thus, the consistent current and voltage are considered over a complete switching duration.According to Figs. 4 and 5, the converter in the CCM can operate in two major modes.In this state, through the KVL and KCL, the voltage and current calculations are realized.

Structure2
In this structure, the position of output inductor and diode has been changed; as a result, discontinuous current output port with positive output polarity has been created.
State 1: When switches are on [0 ≤ t ≤ DTs].The circuit is in this state when power switches S 2 and S 1 are turned ON, while two diodes D 2 and D 1 are in a reversed-biased mode (Fig. 5a).The inductors L 1 , L 2 , and, L 3 are powered by the input source V in through the capacitor C 1 .At this stage, the capacitors C 1 and C 2 are completely drained, leading to an increase in the current flowing through the inductors (i L1 , i L2 , i L3 ).The load resistance Ro is supplied by the output capacitor C o (Fig. 5a).Using the KCL and KVL, the current and voltage equations are achieved.
State 2: When switches are off [DTs ≤ t ≤ Ts].In this state, no power is being supplied by either power switch.Moreover, the capacitors C 1 and C 2 are stimulating, the inductors L 1 , L 2 , and L 3 are demagnetized, and the two diodes D 2 and D 1 are in conduction mode (Fig. 5b).It should be noted that the inductor L 3 feeds the output load R o and also charges C o .By the current path of D 1 and D 2 diodes, energy is discharged from capacitors C 1 and C 2 .
In this state, through the KCL and KVL, the current and voltage equations are achieved, (1) The gain ratios of voltage and current relations of the introduced converters presented in Figs. 4 and 5 (State 1 & 2) are derived in this section.With the volt-second balance principle of inductors L 1 , L 2 , and L 3 , the average capacitor voltages C 1 and C 2 : Therefore, the voltage gain is obtained as, The relations obtained below are the same for both structures.Considering there is no circuit loss, the powers of input and output can be calculated by: The current gain is attained based on (6): Using the ampere-second balance principle, the mean current value of all inductor currents is defined by the capacitance C o , C 2 , and C 1 .
The voltage and current stress are calculated for the two power diodes and switches:

Efficiency and power loss evaluation
Various parameters affect the power loss of the presented structures configuration, such as the diode's forward voltage drop and switching frequency, and component internal resistances.To obtain the number of losses in each circuit element, the circuit illustrated in Fig. 6 is used.
Switches and diodes have the following approximate RMS values of structures are: (5) www.nature.com/scientificreports/Moreover, to get the estimated RMS currents flowing through an inductor and capacitor, apply the following equations: In power switches, the total power loss (P S1,2-Total ), is definite as the sum of leading power dissipations (P R-S ) and the switching losses (P S-L ).Assuming R S is the power switch's conduction resistance, we can determine: In addition, by using V FD as its forward bias voltage and R FD as its accelerative conduction resistance, the overall losses of the diodes can also be calculated as the sum of forward (P FD ) and reverse bias losses (P FR ): Two types of losses in inductors: copper losses and core losses.Obtaining the core loss of inductors can be done as follows: In this equation, α, b, and c parameters can be obtained from the data sheets.f, B, l m , and A c are the frequency, half of the ac flux, the core's magnetic path length, and the area of the core, respectively.Considering R C and R L , the following equation can be applied for determining equivalent series resistance (ESR) values of inductors, and capacitors; an inductor and capacitor's copper loss and total loss are defined as follows: ( 14)  www.nature.com/scientificreports/Using R C to determine equivalent series resistances (ESRs) and power losses for capacitors, the following equation can be used: Accordingly, the sum of the power losses resulting from diodes, inductors, capacitors, and power switches constitutes the overall power losses of the suggested converter.
Finally, the efficiency of presented structures: Figure 7 shows the charts in Buck/Boost operation to understand the power losses of each element portion.In the buck operation, the efficiency is determined as less than that in the boost operation.The converter possesses a higher input current compared to the introduced converter output current in boost mode.However, when the step-down mode is on, the output current is higher than the input current.Therefore, compared to the step-up mode, there is a decrease in efficiency in the step-down mode.The power losses of S, D, L and C are determined as ( 18), ( 20), ( 23) and ( 24) in buck/boost mode.

Effect of parasitic parameters on the circuit
The simplified proposed circuit includes parasitic parameters for structure1, such as parasitic parameters of the inductors (L 3 , L 2 , and L 1 ), the capacitors (C 2 and C 1 ), the diodes (D 2 and D 1 ), and the MOSFETs (S 2 and S 1 ), which is represented in Fig. 6.V FD1 and V FD2 represent threshold voltages of diodes.Therefore, the equations for inductor voltages involving parasitic parameters ) can be calculated as follows: State1 :

Determination of the amount of ripple inductors
Ripples in inductor currents i L1, i L2 and i L3 are obtained in Figs.4a and 5a: To strategy the inductors in the proposed converter, the current ripples are measured.Regarding the peakto-peak current (Figs.4a, 5a) and supposing that current ripples in inductors of (33), the needed values of inductances and ripples inductor currents are: Substituting I L1,2,3 from ( 9) to (34), the following relation can be obtained: www.nature.com/scientificreports/For solar panels to extract more power and for fuel cells and batteries to last longer, the input current ripple needs to be suppressed to a rational value 49,50 .Moreover, an inductor's inductance size determines its current ripple limit.Thus, taking into account the maximum satisfactory current ripple for each inductor, the output/ input current ripple magnitudes can be determined for structure1and 2 as follows: The output and input current ripple of L 3 and L 1 variation against duty cycle and switching frequency is shown in Fig. 9.

Drop in voltage of inductor
Across each inductor, a net voltage drop exists caused by the inductor's internal resistance.Based on (37) it should be the percentage of the average voltage drop across each inductor based on the input:  www.nature.com/scientificreports/Across each inductor, the voltage drop as the output voltage percentage is according to the internal resistance, load resistance, and duty ratio.For various duty cycles, Fig. 10 shows the voltage drop through individually inductor as a percentage of the output voltage for different Duty cycle (0.2, 0.4, 0.6, and 0.8).Voltage drops across the inductor are similar at low-duty cycles, while at high-duty cycles, voltage drops increase with the source.The reason is that the input current is very high at a higher duty cycle value.

Operation of proposed converter in DCM
The suggested converter works in Discontinuous conduction mode (DCM), So that current of the diode D 2 comes to zero some time before the begin of the another exchanging cycle.The DCM configuration plot and key waveforms of the suggested converter for DCM operation are portrayed in Figs.11 and 12, respectively.The operation of the proposed converter can be partitioned into third states.The states 1 and 2 are equal to the CCM operation and the state3 (DCM operation), all the switches S 1 , S 2 and diodes D 1 , D 2 are turn off.
By using the current and voltage Eqs. ( 3)-( 4) in DCM, the voltage gain is obtained as, Again, by utilizing the principle of current-second balance to the capacitor C o , the following equation is derived.
By using ( 38) and ( 39), γ is calculated as, From ( 38) and ( 40), the voltage gain in DCM is obtained as,  where the inductor ( Due to the dependence of the DCM converter's voltage gain on its parameters and the high input current ripple, DCM operation is typically not advised.

Determination of boundary condition
Boundary conditions of the proposed converter can be obtained by equating M CCM = M DCM .It is essential to design the discrete inductors that must guarantee the continuous conduction mechanism for the presented converter.Taking into account the aforementioned necessity, the condition of CCM is determined in terms of the alternative circuit (Figs.4a, 5a) for inductors L 1 and L 2,3 , using the following: The τ LB (boundary condition) for L 1, L 2 , and L 3 are as follows.Moreover, the area over each curve of Fig. 13 is the continuous conduction mode and the area below represents the discontinuous conduction mode, which are as follows:  Also, based on the following conditions, the capacitances of each capacitor can be obtained as: It is necessary to decrease the voltage ripple of the output capacitor to a reasonable level in order to stabilize the transferred power to the next part of the circuit and extend the lifespan of the components.Moreover, the voltage ripple limit of a capacitor is based on its capacitance size.The voltage ripple of C 1 and the output capacitor voltage ripple are achieved as follows: The voltage ripple of C o and C 1 variation against the duty cycle and switching frequency is shown in Fig. 14.

Calculation of duty cycle
It is possible to calculate the duty cycle in order to determine the desired output voltage given an input voltage.Based on ( 6) is obtained:

Small signal modeling
The equations of the dual states from Fig. 4a and b (structure1), can be calculated by: ( 43) www.nature.com/scientificreports/This state-average model 51 can be simply obtained using the averaging method and Eq. ( 49): and v in respectively.In order to derive the small signal model, the small AC values of the elements mentioned above must be determined as follows: i L3 , i L2 , i L1 , v c0 , v c2 , v c1 , v in and d .Besides, the associations among mean, AC, and DC values can be obtained as follows: To obtain AC and DC values and remove the high-order small signal terms, we substitute ( 52) into ( 51) and ( 50): www.nature.com/scientificreports/ The V o matrices can be obtained: To verify the model, the extracted bode diagrams from the calculation process and simulations are illustrated to control the output transfer function (Fig. 15).The parameters in Table 3 are utilized to sketch the bode diagrams.As seen, there is a good consistency between the calculated model and the results of the simulation.Therefore, the proposed model can be utilized for precise controller design and dynamic analysis.Based on the gain and phase margins, Fig. 16 shows the control system parameters using the SISOTOOL toolbox in MATLAB.The PI controller can control the V o at 72 V and 15 V in step-up and step-down modes.Nevertheless, when the load is altered in an open-loop control system, the ripples in the output voltage change.
The small-signal dynamic response of the suggested converter for given perturbations in duty cycle, control input, input voltage and change in output load resistance is plotted in Fig. 17.The suggested converter has a good dynamic behavior over a small perturbation.

Comparison with existing converters
Table 1 the comparison of structure 1 and 2 is presented.An overview of the suggested semi-quadratic converters and other existing converters is shown in Table 2.As observed, semiconductor element number was evaluated as well as switches' voltage stress, voltage gain ratio, SDP avg /P o , output polarity, voltage stress of diodes, and continuous output/input current port for the presented converter and other converters.Although the presented structures in this case have a continuous input current and fewer semiconductor elements, it can certainly be a suitable option for PV inverters due to its continuous input current.With ten elements, high voltage gain ratios and the designed configuration structure1 includes continuous input/output current ports.The superiority of the presented structures is shown as below:

Voltage gains comparison
Comparing the voltage gain ratios is shown in Fig. 18, while Table 2 lists competitor converters and the data they provide.The considered converter provides a larger voltage gain than similar converters when D > 0.5.As seen, the horizontal axis indicates the duty cycle (20-90%).Furthermore, the vertical axis represents the output voltage over the range of 0-15 V.The higher D and V o , but at the expense of more loss of power.

Effectiveness index
Here, the proposed structures performance is assessed with other buck/boost converters for validating the aforementioned properties.In Table 2, a detailed comparative analysis is presented based on the maximum voltage stress on diodes, common ground characteristics, voltage gain, input/output current ripple, the voltage stress on switches, and the overall number of elements.Furthermore, an efficiency index (EI) is presented for evaluating the ratio between the whole number of used elements and the voltage gain value 22,23 .EI is calculated as follows:

Positive
Yes/Yes

Positive
Yes/Yes

Negative
Yes/Yes

Negative
Yes/Yes This parameter accurately depicts the converter's power density and optimal circuit element use. Figure 19 shows the EI plotted against duty cycle for the converter that is being shown and several comparable converters.

Voltage stress on elements
As shown in Fig. 20a the electrical voltage stress on the semiconductor switches S 1 and S 2 for different input voltage.In Fig. 20b, the voltage stress on diodes D 1 and D 2 are compared.I can be seen, that the voltage stress on the switch S 2 and diode D 2 of the proposed converter is higher than other similar converters, but finally the switching device power (SDP) of proposed converter is lower than other converters as shown in next section.Additionally, in most conventional topologies, the voltage stress on capacitors C 1 and C 2 is identical, and hence, the result can be observed from Fig. 20c and d, where nearly all topologies have the close and same voltage stress on capacitors C 1 and C 2 .In Fig. 20e, the voltage stress on switches and diodes of the proposed structures is shown.

Total SDP
SDP is an appropriate index to evaluate different features of switching devices like cooling system necessities, potential costs, and losses 48,52,53 .When evaluating the power loss and the ultimate cost of implementation of a converter, voltage stress and current of its switches and diodes are considered.Therefore, it is necessary to investigate such stresses.As discussed previously, SDP can help calculate the cost and power loss of the converter.The overall average of SDP (SDP avg ) is determined as follows: In which, I Savg_i and V S_i denote the average current and peak voltage of a switching period of the i th semiconductor of the converter.For different converters, the total average SDPs is represented in Fig. 21.Compared to similar buck/boost converters, the presented converter achieves lower SDP, which directly leads to lower semiconductor costs and power losses.During buck/boost operation, the total average SDP is determined as follows:

Experimental result and building a prototype
Experimental simulations and examinations of the presented buck-boost structure1 proved the validity of the theoretical models and experiments for both operation modes.
A list of the elements used in simulation and experiments on the presented converter is shown in Table 3.These parameters were selected using Eqs.( 44)-( 46) and ( 33)- (35).The current variations of inductors were set at 30%, and the voltage ripples of capacitors C o , C 2 and C 1 were regulated at 0.5%, 2% and 2%, respectively.The ripples of capacitor voltage were considered to calculate the capacitance of C o , C 2 and C 1 using Eqs.( 44)- (46).The inductance of L 3, L 2 and L 1 was selected in terms of the inductor current ripples (33)- (35).When the converter is operating in step-up mode, its voltage input level can be adjusted within the range of 20 V dc to 72 V dc and with negative polarity.The inductor current waveforms for L 3, L 2 and L 1 are displayed in the CCM mode along with the converter input continuous current.Furthermore, considering the input voltage of 20 V and duty cycle of 0.534, the mean current of inductors L 3, L 2 and L 1 is 1 A, 1.13 A, and 2.52 A respectively.Based on Eqs. ( 5) and ( 6 of switch and diode.The average current of inductors L 3, L 2 and L 1 is 1A, 0.32A, and 0.41A, respectively in stepdown mode, by the input voltage of 20 V and the duty cycle of 0.245.Furthermore, the quantity of voltage stress applied on capacitors C o , C 2 and C 1 is 14.98 V, 35.07 V, and 26.47 V, respectively.Besides, based on the analytic equations, the voltage stresses applied on switches and diodes are 26.41V, 20.01 V, − 61.71 V, and − 26.58 V, respectively.Figure 22 shows the simulation waveforms of the structure1 under CCM mode operation via the PLECS in the boost and buck operation.It represents the current and output voltage, gate-source voltage, diodes voltage and current, and switch voltage of the MOSFET.

Building a prototype and performance evaluation
Here, to verify the aforesaid properties of the suggested structures, an experimental prototype is used.The prototype was run and examined with 15W (buck mode) and 72W (boost mode) output powers.Figures 23 and 24 show the experimental prototype and driving circuit.The circuit elements corresponding to the experimental converter are presented in Table 3.According to Table 3, the power switches are two MOSFETs (IRFP4668PBF).SR5200 diodes were selected for realizing the diodes.The photocoupler TLP250 was utilized to drive the switches S 2 and S 1 .
The experimental waveforms of the experimental prototype are shown in Figs. 25 and 26 (structure 1), which were recorded and measured via a GW INSTEK GDS-2102A oscilloscope, GW INSTEK GPS-4303 power supply and a Pintek PA-667 1 MHz current probe.Figures 25 and 26 represent the converter operation and the accuracy of the mathematical model via the experimental prototype.Moreover, the waveforms of the voltages and currents of the intended converter in dual modes are displayed.These standards were measured in the laboratory.Results from the PLECS simulations and experiments differed very slightly.Finally, the test results proved that the operation of the converter as presented is completely valid, verifying the principles of process and features outlined earlier.The experimental and theoretical proficiency curves of the proposed converter are displayed for varying output power in Fig. 27a and b for buck and boost operation respectively.A theoretical and experimental analysis of buck and boost operation modes is shown in Table 4 (structure1).A voltage gain for the presented converter is presented in Fig. 28

Conclusion
In this paper, two new transformerless DC/DC buck/boost converters for PV application are introduced.So the features proposed structures has semi-quadratic type buck/boost conversion, common ground, minimal ripples comparable to those in the Cuk converter at output and output sides (structure1), high voltage gain, and negative and positive output load voltage polarity for structures1and 2 respectively.The operating principle of the presented structures is described and steady-state analysis is performed to obtain the voltage and current relations in the two modes of operation.The efficiency analysis and power loss estimation are carried out considering parasitic elements of the converter.The design of passive elements based on the ripple voltages and currents is discussed.The developed structures performance is evaluated in comparison with similar existing converters and is observed to possess a higher voltage gain ratio, high efficiency, and small SDP than other similar converters.To test and verify the performance of the converter, it has been adjusted at various duty cycle values.The peak efficiency of the converter was 91.8% at 72 W. Considering the features of the designed converter including the continuous output/input current port and negative output polarity characteristics, it can be considered appropriate for applications including renewable energy, multi-function power supplies, signal generators and audio amplifiers.

Figure 1 .
Figure 1.Simple Schematic of application of solar PV system with SPOs.

Figure 4 .
Figure 4. States of operation of the suggested converter for buck/boost mode (Structure1).(a) State 1(switches are ON); (b) State 2(switches are OFF).

Figure 5 .
Figure 5. States of operation of the suggested converter for buck/boost mode (Structure2).(a) State 1(switches are ON); (b) State 2(switches are OFF).

Figure 9 .
Figure 9. Current ripple plot versus fs and D. (a) Output current; (b) Input current.

Figure 10 .
Figure 10.Voltage drop across L 1 , L 2 and L 3 inductors as a percentage of the output voltage.

Figure 17 .
Figure 17.Dynamic response of proposed structure1, (a) Output voltage per change in output load resistance for constant input voltage (step-up mode) (b) Output voltage per change in output load resistance for constant input voltage (step-down mode); (c) Output voltage for small step change in duty cycle (2%) and input voltage (5%).

Figure 18 .
Figure 18.Plot of output voltage gain versus duty cycles.

Figure 20 .
Figure 20.Comparison of Voltage stress, (a) Voltage stress on the switches; (b) Voltage stress on the diodes; (c) Voltage stress on the capacitor C 1 ; (d) Voltage stress on the capacitor C 2 ; (e) Voltage stress on the switches and diodes of the proposed structures.
based on theoretic and experimental outcomes.Voltage gain values achieved experimentally differ from theoretical values due to the parasitic parameters of different circuit elements.

Figure 21 .
Figure 21.Plot of normalized SDP avg vs duty cycle.

Figure 27 .
Figure 27.The efficiency of Experimental and theoretical result.(a) Buck Operation; (b) Boost Operation.
Structure1The inductors L 3 and L 1 in the output and input terminals of the suggested converter ensure output/input current continuity.
in through the capacitor C 1 .At this stage, the capacitors C 1 and C 2 are depleted, resulting in an escalation of current in the inductors (i L1 , i L2 , i L3 ).The load impedance R o is supplied by the output capacitor C o (Fig.4a).Using the KCL and KVL, the current and voltage equations are achieved.State 2: When switches are off [DTs ≤ t ≤ Ts].In this state, no power is being supplied by either power switch.Moreover, the capacitors C 1 and C 2 are charged, the inductors L 1 , L 2 , and L 3 are demagnetized, and the two diodes D 2 and D 1 are in conduction mode (Fig.4b).It should be noted that the inductor L 3 feeds the output load R o and also charges C o .By the current path of D 1 and D 2 diodes, energy is discharged from capacitors C 1 and C 2 .

Table 1 .
Comparison of the proposed structures.

Table 2 .
Evaluation of the suggested structures and the existing converters.

Table 4 .
Theoretical and experimental results comparison.Theo = Theoretical, Exp = Experimental.Significant values in bold.