An optimized DCO with modified binary-weighted DCTLs based hybrid tuning banks for an E-band DPLL

An optimized millimeter-wave digital controlled oscillator (DCO) in a 40-nm CMOS process is presented in this work. The coarse-tuning modules and medium-tuning modules of the DCO utilize modified binary-weighted digitally controlled transmission lines (DCTLs) to achieve a better compromise among smaller chip size, higher resonant frequency, better tuning resolution and lower phase noise. The tuning precision and die size of the medium tuning bank are improved without changing the binary coding rules by replacing the lowest-weight bit of the DCTLs with switched capacitors. In comparison with traditional DCTLs, the control bits of the coarse and medium tuning modules have been changed from 30 to 8, resulting in a 34.4% reduction in overall length (from 122\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu$$\end{document}μm to 80\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu$$\end{document}μm). In addition, the DCO’s fine-tuning modules are achieved using a binary-weighted switched capacitors array connected to the secondary winding of a low-coupling transformer, which enhances the DCO’s fine-tuning bank for better frequency resolution with less circuit complexity. The measured tuning range of the optimized DCO is 76-81GHz with a smaller die size of 0.12mm\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$^2$$\end{document}2. This results in an outstanding figure of merit (\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$FoM_A$$\end{document}FoMA) of − 190.52dBc/Hz.


Design and implementation of the circuit
Figure 2 shows the circuit topology of the E-band DCO, consisting of coarse tuning bank (CB), medium tuning bank (MB) and fine tuning bank (FB).The CB is based on 4-bit modified binary-weighted DCTLs, while MB consists of 3-bit modified binary-weighted DCTLs and 1-bit switched capacitor.Additionally, the FB is composed of a 4-bit switched capacitor array connected to the secondary coil of a low-coupling transformer.

Coarse & medium tuning modules
The equivalent schematic of CB and MB based on binary-weighted DCTLs is illustrated in Fig. 3. Since the proposed DCTLs change the number of capacitors connected to the tuning bank by changing the effective dielectric constant via MOS switches, this operation controls the resonant frequency at discrete frequency points according to different control codes 12 .With CM or MB connected to the circuit by the MOSFET switches, the characteristic impedance is calculated as Where L 0 is the equivalent inductance of the transmission lines' per unit length, C 0 is the coupling capacity between two parallel transmission lines and the capacitive coupling between the transmission lines and the substrate.C M is the Metal-Insulator-Metal capacitance between the floating strips and the transmission lines.
As shown in Fig. 4, unlike the traditional thermometer-coded DCTLs, the floating strips used in these modified DCTLs are selectively optimized rather than strictly binary-weighted, resulting in the most linear effective dielectric constant to overcome the non-linearity problem.The CB based on the proposed DCTLs achieves a total reduction in length of 31.8% (from 91µ m and 62µm).Similarly, the control bits of the MB (excluding the lowest weight control bit of the MB consisting of the switched capacitors) are reduced from 15 to 4, achieving a 41.9% length reduction (from 31µ m to 18µm).The passive component loss and the fixed parasitic capacitance are reduced, while the overall Q-factor of the proposed DCTLs is increased (Q=14∼ 16 @78GHz).
Figure 5 displays the structure of the hybrid modified binary-weighted DCTLs based MB.The switch capacitors are used as the lowest weight bit of the medium-tuning precision control codes, which overcomes the tuning precision limit of the DCTLs-only tuning modules without changing the binary encoding rules.At the same time, this technique reduces the die size of the MB and the impact of parasitic devices on circuit performance.
Table 1 demonstrates the comparison of the control bits between the thermometer-coded DCTLs and the proposed DCTLs applied in the CB.The tuning modules utilizing modified binary-weighted DCTLs can achieve a high resonant frequency and broad frequency tuning range with a reduced number of control bits, resulting in a more condensed chip size.

Fine tuning module
The simplified equivalent schematic of the FB and the low coupling coefficient transformer is shown in Fig. 6.The FB is achieved by using an array of binary capacitors connected to the secondary coil of the transformer to promote frequency resolution while reducing circuit complexity, as opposed to the typical Class F VCOs that focus primarily on enhancing the third harmonic and extending the tuning range [13][14][15][16] .
The rate of change of L eq with the respect to the equivalent capacitance C L of the FB can be expressed as (1) Where k is the coupling factor of the transformer.L p and L s are the respective inductances of the coils of the transformer.
The design of the transformer is a crucial part of the overall DCO and particular attention should be paid to the coupling coefficient and the Q-factor.The lower coupling coefficient k allows L eq to increase smoothly and linearly with the increase in C L , as shown in equation ( 2). Figure 7 shows that the Q of the two transformer coils at the operating frequency is above 15 and the coupling factor of the transformer is below 0.25.To minimize the frequency tuning step, the coupling coefficient of the transformer k is set to 0.21.In addition, the detrimental effects of parasitic capacitance in the tuning bank can also be reduced by using a coupled transformer with such a small k [17][18][19] .The binary-weighted array of switched capacitors connected to the transformer's secondary coil can be used to achieve smaller fine-tuning steps.Figure 8 shows that when the equivalent capacitance of the switched capacitor array ( C L ) is between 12fF and 23fF and the equivalent parallel resistance ( R L ) is between 560 and 2200 , the corresponding equivalent tank inductance ( L eq ) is between 49.28pH and 49.38pH.This     www.nature.com/scientificreports/means that a large variation in C L is converted into a small variation in the inductance of L eq by the transformer coupling technique.

Measurements
The optimized DCO was integrated into an E-band DPLL and fabricated on a 40 nm CMOS process as shown in Fig. 9.As shown in Fig. 10, the performances of the DCO were measured using high frequency GSG probes, spectrum analyzer and phase noise analyzer.The die area of the DCO core is 0.48mm×0.25mm.Figure 13 exhibits the measured results of the DCO's spectrum and phase noise spectrum.The DCO is tuned to oscillate at 76-81 GHz.The phase noise of the output signal at 10MHz offset is − 116.72dBc/Hz at 77GHz.The power dissipated of the DCO core is approximately 21.5mW at 0.9V supply voltage.The hump in the phase noise curve is caused by the up-conversion of the power supply noise by the DCO's the cross-coupled amplifier, which creates multi-frequency peaks near the oscillation frequency.The DCO achieves the required metrics for the DPLL system and is able to meet the system requirements.
The proposed DCTLs result in a 34.4% reduction in the overall length of the CB and MB, while maintaining a high Q-factor (14∼ 16 @78GHz), suggesting that it is not necessary to increase the inductor size excessively to prevent phase noise degradation of the resonant tank.As a result, the die area of the proposed DCO is reduced to some extent.Table 2 shows that the above features help to achieve an excellent balance between die size, phase noise, frequency resolution and resonant frequency, resulting in exceptional FoM and FoM A 20 , especially in terms of die area.

Conclusion
A millimeter-wave DCO has been fabricated on a 40-nm CMOS process, featuring a trade-off among chip size, phase noise, frequency resolution, and resonant frequency.The MB and CB, which are based on binary-weighted DCTLs, and the FB, which is a binary-weighted switched capacitor array connected to the secondary winding of a low-coupling transformer, are integrated into the DCO's resonance tank.The modified DCO reaches a high FoM A of -190.52dBc/Hz with a resonant frequency range from 76 to 81GHz, while the frequency resolution is 2MHz.
∂L eq ∂C L = L p L s ω 2 k 2

Figure 2 .
Figure 2. Architecture of the E-band DCO with modified binary-weighted DCTLs based hybrid tuning banks.

Figure 5 .
Figure 5. Layout of the DCTLs in MB with switching capacitors.

Figure 6 .
Figure 6.Simplified equivalent model of the FB fine tuning bank.

Figure 9 .
Figure 9. Chip micrograph of the DPLL containing the DCO.

Figure 10 .
Figure 10.Schematic diagram of the DCO measurement setup.

Figure 12 .Figure 13 .
Figure 12.Measured (a) fine-tuning characteristic and (b) DNL of the CM and MB.

Table 1 .
Simulated C/bit of (a) 4-bit switch of the improved DCTLs for CB and (b) 15-bit switch of the conventional DCTLs for CB.