Lifetime estimation of thin-film transistors in organic emitting diode display panels with compensation

Oxide semiconductor thin-film transistors (TFTs) are used in the pixel array and gate driver circuits of organic light emitting diode (OLED) display panels. Long-term reliability characteristics of the TFTs are a barometer of the lifetime of OLED display panels. The long-term reliability of the driver TFTs is evaluated in a short time under high voltages and high temperature for an accelerated degradation test. If reliability parameters from the power law or stretched-exponential functions are the same for individual devices and devices in an operating panel, the lifetime of the panel can be accurately estimated. However, since compensation circuits are designed into operating panels, an environmental discrepancy exists between the accelerated test of single devices and the operation of devices in the panel. Herein, we propose a novel compensation stretched-exponential function (CSEF) model which captures the effect of the threshold voltage compensation circuit in the panel. The CSEF model not only bridges the discrepancy between individual devices and panel devices, but also provides a method to accurately and efficiently estimate the long-term lifetime of all display panels that utilize compensation circuits.

Organic light emitting diode (OLED) displays employ thin-film transistors (TFTs) in their active pixel array and in-panel gate driver circuits.Several types of pixel circuits exist depending on the compensation scheme and control signals, but basically all pixel circuits comprise a driver transistor and switching transistor.The driver TFT drives a current through the OLED to control the luminance of the pixel.The current is determined based on the gate-to-source voltage (V GS ) and drain-to-source voltage (V DS ) across the driver TFT, which is controlled using the data signal transferred by the switching TFT and voltage on the source node of the driver TFT.A turn-on voltage and data signal are applied to the gate and drain of the switching transistor, respectively, for a time duration of 1/f/N scan for each frame time (= 1/f), where f is the refresh rate and N scan is the number of pixels along the vertical direction of the display.For example, if the f = 120 Hz and N scan = 2160 for an ultra-high definition television (UHD TV), signals to the switching transistor will be in the order of 3.8 μs every 8.3 ms.Pixel transistors are fabricated using oxide semiconductors or low-temperature polycrystalline silicon (LTPS).Oxide semiconductors exhibit good large-area uniformity up to generation 11 glass substrates (2940 mm × 3370 mm in size) making them suitable for large-screen displays in OLED TVs 1-3 .Moreover, oxide semiconductors also exhibit ultra-low off-state current (< 10 −15 A) necessary for low-power energy-efficient displays in smartphones and smartwatches, where they are used in tandem with LTPS [4][5][6][7] .During operation of the display panel, the threshold voltage (V T ) of the driver TFT shifts owing to electron trapping in the gate dielectric, and intrinsic defects in the channel material such as peroxy linkage or undercoordinated metal cations [8][9][10][11][12][13] .Any shift in the V T (ΔV T ) leads to brightness droop over time or brightness non-uniformity across the panel area.Therefore, ensuring satisfactory long-term reliability of TFTs is crucial with respect to the lifetime of OLED displays.Typically, TFTs are fabricated independently and subjected to harsh stress conditions (higher voltage, higher temperature) than normal operating conditions to accelerate degradation and assess reliability in a reasonable test time.This method is used as a proxy for assessing reliability of TFTs in a panel to estimate the panel lifetime during normal operation.Time dependence of ΔV T of a single device is generally described using the power law, �V T (t) ∝ t b , or the stretched-exponential function (SEF), which are used to depict the long-term reliability of the OLED panel 14,15 .If the parameters from ΔV T (t) of an individual device were the same as those of TFTs in a OLED panel, then this connection between individual TFTs and panel TFTs would not be an issue.However, in addition to the different voltage conditions between individual TFTs and TFTs in the panel, we discovered that the correlation begins to collapse when the devices and panel circuitry become increasingly more intricate.The most striking difference is that V T compensation circuits are put in place for the driver TFTs in a panel environment 3,16,17 .Hence, the discrepancy between the accelerated stress measurement of an individual TFT and the long-term reliability of the panel is inevitable.Closing the gap between the reliability test of individual devices and panel devices is challenging; however, minimizing this discrepancy is important for ensuring accurate panel lifetime estimation.In this study, we identify this discrepancy and propose a compensated stretched-exponential function model that correctly captures the degradation of panel TFTs including the effect of the compensation circuit.By using this model, we can accurately estimate the long-term lifetime of display panels in a shorter time than conventional methods.

Identification of inconsistency between individual device and panel device tests
The reliability of oxide semiconductor TFTs is a crucial factor that determines the lifetime of a display panel.The lifetime of display panels (e.g., commercial televisions) operated under normal usage should be 10 years or more.The failure of a display panel may occur due to long-term degradation of the OLED (due to aging and/or chemical damage) or the electronic devices controlling the OLEDs.The lifetime of the display panel is determined based on the failure of the OLED or TFT, whichever occurs earlier.This study focuses on the lifetime of the oxide semiconductor TFT backplane.The critical lifetime of the TFT is realized when the worst-case V T reaches V T (τ life ) = V T (t = 0) + ΔV T,limit , where ΔV T,limit is a predetermined value set depending on the upper limit the compensation circuit can effectively operate and accurately compensate the ΔV T .Owing to the slow degradation process, accelerating the degradation by testing the devices under high voltages and temperatures in a matter of hours is a common practice.However, the correlation between the accelerated reliability test of a single TFT device and the lifetime of an OLED panel fails when the panel and devices become increasingly complex.Hence, the panel lifetimes are often extrapolated from electrical measurements of panel degradation over months-long test operation.Finding the reason behind this discrepancy and validating a consistent and quantitative correlation between device and panel lifetime is crucial in significantly shortening the panel evaluation time and accurately representing the TFT array in a panel environment.
Figure 1 shows the ΔV T with respect to TFTs in an operating display panel under different gray levels up to 1500 h at room temperature.The gray level is defined as the digitized brightness level of a pixel, with 0 G being the darkest and 255 G being the brightest level.Gray levels are expressed based on calibrated voltage conditions including gate overdrive voltage V OV (= V GS -V T ) and drain-to-source voltage V DS conditions applied to the driver TFTs.The ΔV T is higher for higher gray levels because the TFTs are subject to high bias stress conditions.Hence, examining whether the device reliability tests correlate to the reliability of TFTs in the pixel array of a panel is extremely important.
Figure 2 shows the ΔV T of an InGaZnO (IGZO) TFT device under DC stress using different gate-to-source voltage (V GS ) and drain-to-source voltage (V DS ) conditions.Symbols in Fig. 2 represent the measured data and the lines represent SEF fitting curves.Table 1 shows the SEF parameters (ΔV T0 , τ, β) for different bias stress (1) �V T (t) = �V T0 1 − e −(t/τ ) β Figure 1.V T shift of transistors in the display panel subject to different gray levels varying from 3 to 255 G, up to 1500 h in a room temperature ambient.Each gray level is determined based on the gate overdrive voltage (V GS -V T ) and drain-to-source voltage (V DS ) applied to the driving transistor, represented in the figure as the first and second numbers in parenthesis, respectively.Difference in gray levels between curves is 21 G apart.conditions.Generally, the extracted τ and β values differ upon how ΔV T0 is defined.ΔV T0 is the saturated value of ΔV T when the TFT has been subject to stress for a sufficiently long time (t → ∞).
When the N OT -limited model is used, we assume that the cause of ΔV T saturation over time is caused by the finite trap density in the interface and bulk of the gate dielectric (N OT ).In this model, ΔV T0 is a constant that is irrelevant to the stress voltage and is determined by N OT present in the device.ΔV T0 is determined based on the maximum ΔV T caused by N OT being completely full of trapped charge.
where q is the elementary charge, C ox is the gate oxide capacitance per area, and t ox is the thickness of the gate dielectric layer.Figure 3a shows the ΔV T (t) of the panel TFTs for different gray levels, where N OT = 3 × 10 17 cm −3 is assumed which gives ΔV T0 = 30 V. All ΔV T (t) curves saturate at the same ΔV T0 value, where hypothetically all the defect states in the GI are filled with trapped electrons at t → ∞.The characteristic time τ in the SEF (Eq. 1) can be extracted using the measured ΔV T (t) for panel and single individual devices (Eq.2).Also, τ follows an inverse relationship with (V OV = V GS -V T ) as expressed in the following equation: where σ 0 is the capture cross section, v th is the thermal velocity, f MB is the Maxwell-Boltzmann distribution function, n s is the carrier volume density, and t act is the thickness of the active channel layer.The calculated τ (Eq. 3) and the τ extracted from panel and individual device measurements using the N OT -limited model are plotted against (V GS -V T ) in Fig. 3b.We discovered that the τ extracted from stress tests of single individual devices agree with the calculations; however, the τ extracted from panel TFTs do not follow the calculated τ-V OV trend, exhibiting noticeably higher values.Hence, the N OT -limited SEF model is not appropriate for predicting the lifetime of TFTs in a display panel.
In the electric-field-limited model, the ΔV T saturates due to the weakening of the electric field across the gate insulator.This is because the V T shifts positively under stress owing to the trapped charge while V GS is constant, hence decreasing V GS -V T (t) over time.In the electric-field-limited model, we define Hence, ΔV T0 is dependent on the stress V GS and initial V T of the device.Figure 3c shows the ΔV T (t) of the panel TFTs for different gray levels using the electric-field-limited model, where devices subject to low V GS -V T (t = 0) saturates at low ΔV T0 values.Figure 3d plots the extracted and calculated characteristic time τ against V OV using the electric-field-limited SEF model.The τ extracted from ΔV T (t) of individual devices under reliability tests

Proposed compensated stretched-exponential function model
Primary difference in evaluation conditions between a reliability test for an individual device and devices in the panel is whether the bias conditions are maintained constant or not.Constant voltage is maintained throughout the stress phase of an instability test of a single individual device.However, OLED display panels have a compensation circuit that compensates the varying V T in real-time, indicating that the bias conditions change dynamically as the V T of devices in the pixel array shift.Hence, we must first determine whether the SEF fitting is fundamentally appropriate for devices in a panel with dynamic V T compensation.
When the V T shifts due to stress or a prolonged period of normal operation, V T can be represented as V T = V T (t = 0) + ΔV T (t), where V T (t = 0) is the initial V T and ΔV T (t) is the time-dependent V T shift.For V GS -V T to be kept constant, the compensation circuit applies V GS + ΔV T (t) instead of V GS to the driver TFT.Thus, the SEF can be modified as follows: from Eqs. 1 and 4, assuming the electric-field-limited case.The ΔV T (t) term is present on both sides of Eq. 6; hence, by rearranging the terms we obtain the compensated stretched-exponential function (CSEF), expressed as follows: Panel TFT SEF (N OT -limited) V GS (V), (Gray) Panel TFT SEF (Field-limited)  www.nature.com/scientificreports/CSEF can be used to extract the τ and β from devices in an active panel with V T compensation.Figure 4a shows the CSEF model fitting to V T shifts of devices in a panel for various gray levels up to 3600 h at room temperature.First, we implement the CSEF model to devices on the display panel with a constant brightness represented by a gray level ranging from 24 to 255 G.The measured V T (t) of TFTs in the panel with respect to various constant gray levels are overlaid on top of CSEF model curves with parameters τ and β corresponding to each gray level in Fig. 4a.Table 2 lists the CSEF parameters for various brightness levels.The CSEF parameter τ values from the panel TFTs are plotted against V GS -V T juxtaposed with those of individual TFT devices on the same plot in Fig. 4b.The modified τ extracted from panel devices now follows the inverse relation with (V GS -V T ), justifying the hypothesis that indeed the compensation was the cause of the discrepancy between panel devices and individual devices.The validity of the CSEF model is proven, having τ extracted from both single individual devices and panel devices being in agreement on a universal τ-V ov curve (Eq.3).By selecting a SEF model based on the stress/operation concept of the device under test, we can maintain consistency between data obtained from standalone devices and devices within a panel.For TFT devices with no compensation the standard SEF model is used, while for TFT devices in a panel with compensation circuit operation the CSEF model is used.

Verification of the CSEF model via various display data patterns
Having established the CSEF model, it is necessary to verify its validity for TFTs in the panel for various data patterns.To emulate a display operation environment rather than a constant DC stress bias, we select rolling patterns between 5 gray levels and an on and off pattern with a duty cycle of 50%.To model the ΔV T (t) for TFTs in the panel subject to different patterns, a systematic approach must be adopted.Figure 5a-c show how the ΔV T (t) can be obtained for an arbitrary pattern by adjoining ΔV T (t) segments each with a constant gray level for a certain duration.Each pattern segment corresponds to a gray level that is correlated to data bias conditions (V GS,i , V DS,i ) for a particular pattern duration (Δt i ).The ΔV T (t) during an arbitrary pattern segment can be expressed as: where F(x) represents the ΔV T (t) from the panel pattern, and f i (t) represents the individual ΔV T (t) for a specific gray level condition corresponding to the voltage pulse V GS,i between t i-1 to t i (Δt i = t i -t i-1 ).Each pattern segment uses one set of CSEF parameters corresponding to the constant gray levels, as listed in Table 2.The degradation history of V T caused by the data pattern up to that current point is reflected, by keeping the final ΔV T value of ( 7)   www.nature.com/scientificreports/ the previous segment as the initial value of the current segment.Furthermore, since ΔV T (t) is updated and not reset after each segment, the change in degradation rate is also considered.For example, the first few segments can be expressed as: and so on.By using this method, we can replicate the ΔV T of panel TFTs experiencing complicated data patterns.Figure 5d-f show the application of the CSEF model using Eq. 8 for a rolling pattern of 5 gray levels for 3600 h using three different gray level combinations.Figure 5g-i show the application of the proposed method on a panel under an alternating on and off pattern with a duty cycle of 50%.We can observe that the ΔV T (t) measurements and model results are in good agreement, validating the panel data pattern-dependent CSEF model.We can accurately predict the panel lifetime under arbitrary complex display patterns using CSEF model parameters obtained from measurement data of panel TFTs under various gray level conditions.

CSEF model with V T0 variation using empirical V T0 -dependent τ model
Owing to the amorphous nature of oxide semiconductors, it is inevitable but to have a statistical variation in device properties across the large glass substrate spanning over 3 m on one side.Based on the verified panel data-dependent CSEF model, we analyze the initial V T (= V T0 ) distribution in the CSEF model, specifically by establishing a relation between V T0 and τ. Figure 6a shows the ΔV T of 24 panel devices with variation plotted against V T0 .The devices are operated at a constant gray level for 3600 h.Despite maintaining a constant V OV throughout the operation with the help of the compensation circuit, a positive correlation between ΔV T and V T0 can be observed.This shows that devices with high V T0 will most likely result in high ΔV T .Figure 6b-d show the ΔV T (t) of 24 devices in the display panel at a constant brightness level (only few selected gray levels are shown).( 9) www.nature.com/scientificreports/In Eq. 3, any change in V T0 does not affect n s because compensation corrects any ΔV T (t) and variation in V T0 to ensure that V OV is kept constant.Even under the same intended fabrication process, the local spatial variation in process conditions influence the film properties and the device characteristics, causing variation in V T0 .Process factors that vary V T0 could also influence the trap properties.Particularly, we assume V T0 affects the capture cross-section σ, and an effective V T0 -dependent τ(V T0 ) is introduced.When we use the V T0 -dependent τ(V T0 ) in the CSEF model as in: the model captures the ΔV T (t) including V T0 variation, which agrees with measured values with respect to different gray levels, as shown in Fig. 6b-d.Average τ and β values obtained from the CSEF model of 24 devices are listed in Table 3.To find the functional form of τ(V T0 ), variation in τ values are plotted against V T0 as shown in Fig. 6e-g.We implement an empirical equation in the form of τ = a 0 • V T0 b 0 , where a 0 and b 0 are used as fitting parameters.These fitting parameters for each brightness level are listed in Table 3.For a higher V T0 , τ becomes smaller because b 0 < 0 (and a 0 > 0) which leads to ΔV T (t) increasing rapidly at an earlier timescale.a 0 is smaller and b 0 has a less negative value for a higher ΔV T0 which corresponds to a smaller τ value that is less sensitive to V T0 at a higher gray level.Our proposed CSEF model can be useful in estimating the lifetimes of display panels including the effect of V T0 variation of the TFT devices.

Discussion
Conventionally when evaluating the lifetime of the panel, the power law or SEF are used to model ΔV T (t) of TFTs.We have demonstrated that the CSEF model represents driver TFTs more accurately under a V T compensation scheme compared to the SEF model.Herein, we quantitatively compare the functional form of the power law ( �V T (t) = a • t b ), SEF (Eq. 1),and CSEF (Eq. 7). Figure 7a shows the three models as a function of time.Since (12)

∆V
T (V) V T0 (V) t stress = 3600 hours V GS -V T0 = 0.76 V (66 G) V GS -V T0 = 2.17 V (150 G)  www.nature.com/scientificreports/b and β determine the slope of the functions in a log-log plot, we equate them to be the same value, b = β.We note that when t ≪ τ, the functions approximately overlap.When t ≪ τ and 0 < β < 1 are satisfied, the SEF can be approximated by the power law, as in asymptotic power laws 18,19 .The power law is not based on physical parameters; it is a mathematical approximation of the SEF.Because the power law has a simple form, it is often widely employed in the industry instead of SEF.Conversely, when time becomes comparable to or larger than τ, the curves differ from one another in the following order: ΔV T,CSEF > ΔV T,powerlaw > ΔV T,SEF , where SEF saturates at ΔV T , SEF (t → ∞) = ΔV T0 .For TFTs in display panels, we observe that the CSEF describes and reproduces the panel measurement data, and CSEF parameters follow the same V OV −1 relation as followed by the SEF parameters of individual TFTs.As shown in Fig. 7b, when the panel lifetime is short, the selection among the three models may have less importance.However, as a longer product lifetime is desired, and the TFTs and circuit schemes become increasingly sophisticated, stable, and robust, the SEF or power law underestimates the ΔV T when extrapolated beyond measurement data, thus posing the risk of overestimating the lifetime of the display panel.
The stress conditions for reliability evaluation with respect to individual TFTs and panel TFTs are different in voltage and temperature levels, as well as operating methods.Hence, a discrepancy is observed in ΔV T progression.Moreover, owing to the absence of an appropriate model, panels are subject to long testing times of up to thousands of hours.We have proposed a novel CSEF model that captures the ΔV T (t) of TFTs in a panel with V T compensation circuits.The proposed CSEF model is verified by comparing the measurement data of ΔV T (t) up to 3600 h.Additionally, the efficacy of the proposed model is proven by accurately estimating the ΔV T (t) of TFTs in a panel with respect to different data patterns.We can shorten the panel lifetime evaluation time to the amount of time required to extract CSEF parameters from panel TFTs at various gray levels, estimate the lifetime of panels under various arbitrary display rolling patterns, and extend the range of lifetime estimation far beyond conventional extrapolation methods.Furthermore, the CSEF model does not overestimate the panel lifetime as opposed to the widely-used power law or the standard SEF.Thus, using the CSEF model for estimation would be more rigorous, especially for panels with long lifetimes.

Methods
Self-aligned top-gate structure amorphous IGZO TFTs are fabricated herein 10 .First, a bottom metal layer is deposited on the glass substrate to serve as a light shield, followed by the deposition of a SiO 2 buffer layer via plasma-enhanced chemical vapor deposition (PECVD).The semiconductor active layer is formed via DC sputtering of a-IGZO (In:Ga:Zn = 1:1:1), followed by gate stack formation comprising a SiO 2 gate insulator formed by PECVD, and a Cu gate formed via sputtering.During patterning of the gate stack, the dry etch and plasma treatment forms the highly conductive source/drain access regions.Interlayer dielectric is deposited by the PECVD of SiO 2 , and contact holes are formed for Cu S/D electrodes to fill via sputtering.The source node of the driver TFT is electrically connected to the light shield layer.A SiO 2 passivation layer is deposited by PECVD.Width and length of the devices are 18 μm and 8.5 μm, respectively.Electrical properties are measured using a semiconductor parameter analyzer (4156C, Agilent).V T of the individual TFTs are extracted where I D = 5 nA from the saturation current characteristics at V DS = 10 V. Stress conditions for the reliability tests of the standalone individual TFTs are V GS = 20-30 V and V DS = V GS + 5 V to ensure saturation operation at room temperature.Stress time is 4 × 10 4 s and recovery time is 10 4 s.
For the panel evaluation, V T (t) of the driver TFT in the pixel is recorded for 3600 h, for constant brightness of various gray levels and different test data patterns.V T of the driver TFT is obtained from a read-out circuit in the panel.The change in V T is compensated during operation using an external compensation circuit 2 .The panel region is divided into different sections, wherein each section of the panel is subject to either a constant gray level or rolling test patterns.For constant gray levels, the brightness of the white color is varied from 0 to 255 G, with increments of 21 G.For rolling test data patterns, an ON/OFF pattern and a rolling 5-level pattern are used.
CSEF parameters are extracted from the measurement data of panel TFTs by using:

Figure 2 .
Figure 2. V T shift of individual transistors for different V GS and V DS combinations, with time x-axis in (a) log scale, and (b) linear scale.Measurements are represented using symbols and stretched-exponential function (SEF) model values are represented using solid lines.

Figure 3 .
Figure 3. (a, c) Threshold shift (ΔV T ) of IGZO TFTs in the display panel subject to various bias conditions corresponding to a range of gray levels.Symbols represent measurement values up to 1500 h, while solid lines represent modeling results extended to 10 11 s using the (a) N OT -limited model and the (c) electric-fieldlimited model.(b, d) Characteristic time constant τ from reliability tests of individual devices (green squares) and devices in a panel (blue circles).τ values are extracted from SEF using the (b) N OT -limited model and (d) electric-field-limited model.A calculated inverse relationship between τ and V OV is represented by the solid red line.Panel τ values deviate from the inverse relationship under both models.

Figure 4 .
Figure 4. (a) ΔV T of IGZO TFTs in the display panel subject to various bias conditions corresponding to a range of gray levels.Symbols are measured values up to 3,600 h, while the solid lines are fitting curves using the compensated stretched-exponential function (CSEF) model.(b) τ values extracted using the CSEF model for TFTs in a panel with compensation (blue circles) and the SEF model for individual TFTs (green squares).All extracted values follow the Inverse relationship between τ and V OV (red solid line). https://doi.org/10.1038/s41598-023-44684-5

Figure 6 .
Figure 6.(a) Distribution of ΔV T of 24 devices with V T0 variation plotted against V T0 .A positive correlation is consistently observed across different gray levels.V T (t) variation of 24 panel devices operated under selected gray levels: (b) 66 G, (c) 150 G, (d) 255 G. Measurement values are denoted by shapes, and CSEF model curves are shown in solid lines.Extracted τ values from CSEF plotted against V T0 of the devices: (e) 66 G, (f) 150 G, (g) 255 G. Fitted empirical functions of τ are shown in red solid lines.

Figure 7 .
Figure 7. (a) Comparison of the functional form between the power law, SEF, and CSEF model.Exponents of time are set equal (β = b = 0.5).(b) Extraction of the panel lifetime using the CSEF model, power law, and SEF.

Table 1 .
Stretched-exponential function model parameters of an individual IGZO TFT device under DC stress of different bias conditions.
10 7 1.2 × 10 7 9.7 × 10 6 9.8 × 10 6 8.7 × 10 6 1.0 × 10 7 8.7 × 10 6 8.2 × 10 6 7.6 × 10 6 7.3 × 10 6 follow the inverse correlation with V OV .However, τ extracted from panel TFTs do not follow this correlation with the calculated values and exhibit lower values.The field-limited SEF model does not capture the ΔV T (t) for panel TFTs and has weak correlation with that of individual TFTs, and hence cannot be used as a prediction model for the panel lifetime.Therefore, both SEF models do not accurately represent the V T (t) of TFTs in a panel environment, raising the question of whether self-consistency between individual TFT devices and panel TFTs can be achieved.Therefore, if a model could be developed wherein the τ of panel TFTs follows the inverse (V GS -V T ) relation, we could gain confidence that lifetime models between single devices and devices in the panel are consistent.Then, why does the evaluation of TFTs in the panel result in τ values that do not follow the inverse V OV relation?Herein, we propose a novel model to bridge this discrepancy.

Table 2 .
Parameters for panel TFTs at various bias conditions each corresponding to a brightness (in gray levels) using the proposed CSEF model.

Table 3 .
Average of CSEF parameters across 24 TFTs with statistical variation for various brightness levels.Fitting parameters a 0 and b 0 for the empirical functional form of τ = a 0 • V T0 b 0 .