Vertical tunneling FET with Ge/Si doping-less heterojunction, a high-performance switch for digital applications

A vertical tunneling field effect transistor composed of a doping-less tunneling heterojunction and an n+-drain is presented in this paper. Two highly-doped p+ silicon layers are devised to induce holes in an intrinsic source region. Due to employing a double gate configuration and Hafnium in the gate oxide, our proposed structure has an optimized electrostatic control over the channel. We have performed all the numerical simulations using Silvaco ATLAS, calibrated to the verified data of a device with the similar working principle. The impact of the wide range of non-idealities, such as trap-assisted tunneling, interface trap charges, and ambipolar conduction, is thoroughly investigated. We have also evaluated the impact of negative capacitance material to further improve our device switching characteristics. Introducing both n-channel and p-channel devices, and employing them into a 6T SRAM circuit, we have investigated its performance in terms of parameters like read and write SNM. The FOMs such as Ion = 34.4 µA/µm, Ion/Ioff = 7.17 × 107, and fT = 123 GHz show that our proposed device is a notable candidate for both DC and RF applications.


Device configuration, fabrication process, and simulation procedure
Figure 1 depicts our proposed vertical TFET.It includes two cladding layers to induce holes in an intrinsic Ge source region, while to reduce the fabrication process complexity an n + Si drain region is deposited at the top of the structure.The material of the channel region is silicon, too.Because of employing the n + drain and the cladding layer in our doping-less tunneling junction device, we name it NCDL-TFET.The electrostatic integrity of the gate is enhanced by using a 2 nm layer of Hafnium as the gate oxide.All other design parameters are tabulated in Table 1.
Despite the complexity of fabrication process of nanoscale transistors, we suggest a fabrication process flow for realizing NCDL-TFET that, according to the literature 33,34 , practically seems feasible.At the beginning a germanium layer is grown over a silicon substrate (see Fig. 2a,b).With the low-temperature in-situ doping technique, a p + silicon layer, acting as a p-gate, is deposited over the germanium layer (see Fig. 2c).Then a thin isolator layer of SiO 2 is deposited over the silicon layer, following which a U-shaped trench is carved in the cladding layer (see Fig. 2d,e).In the next step, an intrinsic germanium layer is grown in this trench to act as the source region (see Fig. 2f).The layers of intrinsic and n + -doped silicon are deposited to form channel and drain regions, respectively (see Fig. 2g,h).After selective etching of the two above mentioned layers, the high-k gate oxide is deposited (see Fig. 2i).The gate metal is deposited, followed by the deposition of the SiO 2 as the spacer (see Fig. 2j,k).Finally, the source, gate, and drain contacts are connected (see Fig. 2l).
In Fig. 3, we have drawn the extracted I D -V G curve of Ref. 22 alongside the reproduced result of our device simulator, and it can be inferred that a good matching is obtained.Silvaco ATLAS device simulator was employed to assess our device performance 35 .We have used Shockley-Read-Hall (SRH) recombination model, CVT, fermi, and dynamic non-local band-to-band-tunneling (BTBT) models for all the simulations.The charge transport model of drift-diffusion is also activated.Due to the large indirect band gap of silicon and channel thickness of 10 nm quantum confinement model is not incorporated in the simulations.During the calibration process, m e = 0.22m 0 and m h = 0.17m 0 have been utilized.

Simulation results
This section first evaluates the impact of cladding layers on the DC/RF performance of NCDL-TFET.Then, we assess our device performance in the presence of trap-assisted tunneling (TAT) and interface trap charges (ITC), temperature change, and ambipolar conduction.Then, we incorporate a negative capacitance in the design of NCDL-TFET, and its impact on our device performance is investigated.Finally, by designing a p-type dopingless TFET, a 6T SRAM cell is designed and its performance in terms of parameters such as reading and writing static noise margin (SNM) is evaluated.Energy bands diagrams of NCDL-TFET along the A-B and C-D cutlines are depicted in Fig. 4a and b.As it can be inferred from Fig. 4a, no charge transport occurs between the cladding layers and the source region, mainly because of a large valence band offset between the mentioned regions.Figure 4b also depicts that no band-toband tunneling happens in the parasitic tunneling path, which is from the valance band of the cladding layers to the conduction band of the channel.Thermionic emission is also suppressed due to the large band gap of SiO 2 and p + doping of silicon layers.Figure 4c shows the energy bands profile of NCDL-TFET along the EF segment (as displayed in Fig. 1) in the off-state (V GS = 0 V) for two different doping levels of the cladding layer.It can be seen that the higher doping of the cladding layers contributes to a smaller barrier width and a more-abrupt tunneling junction at the source-channel interface.This is mainly because increasing cladding layer doping levels induces more holes in the intrinsic source region.Figure 4d illustrates the energy bands diagram in the on-state

Gate Voltage (V)
Ref [22]  Simulation www.nature.com/scientificreports/(V GS = 0.7 V), indicating that a more-favorable tunneling junction is obtained by using higher level of doping concentration in the cladding layers.According to Fig. 5a, the band-to-band tunneling rate has almost a horizontally uniform profile across the channel.Such a uniformity facilitates having a higher on-state current.The tunneling charge carriers move toward the drain side of NCDL-TFET, as represented in Fig. 5b.
As discussed earlier, the doping density of cladding layers plays a significant role in the modulation of the energy bands profile at the source-channel junction of NCDL-TFET.In Fig. 6a, we have plotted the transfer characteristics of our device for four different values of N Clad .It can be seen that the device with N Clad = 4 × 10 19 cm −3 has a better performance compared with that of its counterparts.In Fig. 6b, the impact of cladding layers doping concentration on the V off , V th , and I on is evaluated.We have defined V off as the gate voltage in which BTBT is triggered.For the calculation of V th , we have employed the constant current method, as mentioned in 23 .Obviously, when N Clad = 4 × 10 19 cm −3 the device shows the best performance with minimum V off and V th and maximum I on of 34.4 µA/µm.Transconductance, given by g m = ∂I D /∂V GS , is another important parameter for evaluating FETs' performance.From Fig. 6c, it can be inferred that increasing N Clad results in higher g m values, which are desirable for high-performance devices in low-noise, high-frequency applications.Another essential RF performance metric of a FET device is cut-off frequency (f T ).It is a function of transconductance and parasitic capacitances of the device.Figure 6d illustrates the impact of N Clad on the f T of NCDL-TFET.According to this figure, a significant frequency of 123 GHz can be achieved with N Clad = 4 × 10 19 illustrating that the role of higher g m is more critical than increased parasitic capacitance.In Fig. 6e, we can see how the amount of N Clad affects the transit time of charge carriers in NCDL-TFET.Transit time, which represents the time it takes for charge carriers to move from the source to the drain side, is inversely proportional to f T , where τ = 1⁄(2π) × f T 36 .The results show that when  Figure 7a shows the impact of channel thickness on the transfer characteristics of NCDL-TFET.Increasing the channel thickness degrades the electrostatic control of the gate, contributing to higher off-state currents.We can see that tripling the channel thickness leads to an increment of I off from 4.94 × 10 −10 to 7.11 × 10 −9 µA/ µm.A slight reduction of on-state current with the increment of the channel thickness is also attributed to the electrostatic control degradation.However, the abovementioned values ensure us quantum confinement has no considerable impact on the on-state current of NCDL-TFET when T C = 10 nm.In Fig. 7b, it is observable that with increasing T C from 10 to 30 nm, the on/off ratio decreases from 6.96 × 10 10 to 2.93 × 10 9 .Moreover, minimum subthreshold swing with ~ 153% increase reaches from 18.42 to 28.24 mV/dec.
Defect at the heterojunctions and multi-phonon excitation at the oxide-semiconductor interface can adversely impact the performance of TFETs 8 .In Fig. 8a, we compare the impact of both non-idealities on the performance of our suggested device.In case (a), we have defined the trap energy (E t ) of 0.2 eV and the trap density (D t ) of 1 × 10 12 cm −3 at the Ge-Si interface and the interface trap density (D it ) of 3 × 10 12 cm −2 eV −1 at the HfO 2 -Si interface 37 , while in case (b), a hetero-oxide interface (comprising of 0.5 nm SiO 2 and 1.5 nm HfO 2 ) has been employed.So, the D it = 3 × 10 11 cm −2 eV −1 was used in the INTERFACE model of the device simulator.The change in the subthreshold swing of NCDL-TFET at the presence of these detrimental effects is shown in the inset of the figure.Figure 8b illustrates that by including both TAT and ITC models I off with almost three decades increment reaches to 4.88 × 10 −7 µA/µm, leading to nearly three decades reduction of the on/off currents ratio from 6.96 × 10 10 to 7.17 × 10 7 .On the other hand, employing a hetero-oxide interface improves the off-state current and the on/off currents ratio.However, it leads to a more complicated fabrication process.
The impact of temperature variation on our NCDL-TFET performance is investigated in Fig. 9a, where we have used temperatures ranging from 300 to 400 K. Since thermal generation of charge carriers plays a significant role in subthreshold conductance, the temperature's impact on the off-state current is more significant than that on the on-state current.However, the I off = 3.65 × 10 −7 µA/µm shows that NCDL-TFET has lower power dissipation than the short channel MOSFET even at temp = 400 K.In contrast, the on-state current remains almost unchanged, mainly because the transmission probability equation defined in Ref. 4 has no direct dependency on the temperature.The inset of Fig. 9a shows that with an 100 K increment of temperature, the SS min increases from 18.42 to 30.51 mV/dec which is still significantly lower than subthreshold swing of MOSFETs.
In order to suppress ambipolar conduction in the proposed device, the drain region of the device has not been heavily doped.As depicted in Fig. 9b, by choosing N D = 3 × 10 18 cm −3 , the ambipolar current (I amb ) is even lower than the off-state current.By one order of magnitude increase in N D the ambipolarity of NCDL-TFET rises about seven decades.As a result, the I on /I amb ratio reaches from 1.29 × 10 13 to 1.25 × 10 6 , exhibiting dramatic reduction of our device reliability.
Comparing the achieved performance of our proposed device with some of the recently published works on the same topic, listed in Table 2, indicates that NCDL-TFET is a notable candidate for CMOS applications.
Paraelectric Hafnium, a CMOS-compatible material, has a high potential to act as a negative capacitance material.Adding materials such as Si 38 , Al 39 , and ZrO 2 40 into paraelectric HfO 2 can be a viable solution to attain ferroelectricity.We have employed yttrium-doped HfO 2 (Y: HfO 2 ) in a Metal-ferroelectric-insulator-semiconductor (MFIS) configuration to enhance our device switching performance, as illustrated in Fig. 10.To evaluate the impact of Y: HfO 2 material on the performance of NCDL-TFET, we first calibrated our device simulator with the extracted polarization curve of 41 (see Fig. 11a).Then, the on-state current is calculated using the procedure explained in our previous work 42 .Figure 11b shows the impact of the thickness of (Y: HfO 2 ) on the I D -V G curve of our proposed structure.It should be noted that although increasing T fe improves the subthreshold swing, it can lead to more considerable hysteresis, which is not a desirable in CMOS applications.The inset shows the extracted values of V th and SS avg , and it can be inferred that the higher values of T fe lower V th and improve SS avg .

Nonlocal BBT electron Tunneling )
1 s  A more pragmatic assessment of a device's performance can be achieved by incorporating it into a familiar circuit configuration.In pursuit of this objective, our attention shifts to a hybrid six-transistor (6T) SRAM cell, depicted in Fig. 12.This configuration comprises four n-channel and two p-channel devices.The p-channel device chosen is a vertical PDL-TFET, designed along the same principles as the NCDL-TFET.According to the device structure exhibited in Fig. 13a, PDL-TFET has an intrinsic silicon source located at the bottom of the transistor, while germanium is employed in the channel and drain regions.All pertinent dimensions, parameter values, and activated models for simulations remain consistent with those utilized in NCDL-TFET simulations, with the exception of gate and source work functions which are assigned values of 4.65 eV and 3.9 eV, respectively.In Fig. 13b, our device simulator's accuracy is validated against simulation outcomes from the device highlighted

Transit Time (S)
Gate Voltage (V)    in Ref. 43 .Additionally, we have plotted the transfer characteristics of PDL-TFET, which shows more-optimum performance for low-power applications.By incorporating both n-channel and p-channel devices, we construct the 6T hybrid SRAM cell using four NCDL-TFET devices (M n1 , M n2 , M n3 , and M n4 ) along with two PDL-TFET devices (M p1 and M p2 ).The stability performance of the 6T hybrid SRAM cell is explored through the examination of different static noise margins (SNMs) and their alterations in response to varying supply voltages (V DD ).To ascertain the SRAM cell's SNM, the voltage transfer characteristics (VTC) of the two cross-coupled inverters are plotted.Various SNM values can be derived as the cell functions in the HOLD, READ, and WRITE modes.When the cell is in a HOLD or data retention state, the word line (WL) remains inactive, ensuring that the access transistors remain off.In this state, the cell retains its data using the cross-coupled inverters.Figure 14a visually presents the properties of the HOLD SNM and their shifts corresponding to different supply voltages (V DD ).Notably, the HOLD SNM diminishes proportionally as the supply voltage decreases 44 .
During the READ operation, the SRAM cell is highly susceptible to noise 45 .Following a READ action, the cell must preserve its state without erasing the stored value.Bit lines (BL and BLB) are prepared for the READ operation prior to activating the word line (WL).The READ SNM of the SRAM cell, observed across various supply voltages, is illustrated in Fig. 14b.The minimal bit line voltage required to alter the cell's state is referred to as the WRITE margin.During the WRITE operation, data bits are transmitted on BL and BLB before enabling the word line.The WRITE action's properties in terms of SNM are portrayed in Fig. 14c.A summary of the HOLD, READ, and WRITE noise margins for different supply voltages is presented in Fig. 14d.Across all scenarios, the noise margin decreases with diminishing supply voltage, rendering the SRAM cell increasingly unstable.

Conclusion
We have suggested a TFET composed of a doping-less tunneling heterojunction and an n + -drain region in a vertical configuration.Due to using heterojunction of germanium/silicon in the tunneling interface, the on-state performance of our proposed device is more robust than Si-based doping-less TFETs.By employing a virtual fabrication process, we have shown that our structure can be realized in a feasible and convenient manner.Using Silvaco ATLAS, we have assessed the effect of non-idealities, such as defects at the tunneling interface and temperature, on our device performance.Our proposed device offers high scalability, sub-60 mV/dec performance even in the presence of defects, and higher AC performance than conventional doping-less TFETs.Although, using n + doping in the drain region can increase the thermal budget but effectively reduce gate-to-drain parasitic capacitance and reduce fabrication steps.Moreover, silicide formation is no longer a challenge due to using highly doped cladding layers instead of inductive metal.We have also utilized yttrium-doped Hafnium as a negative capacitance material in an MFIS configuration, and a considerable improvement without any hysteresis was obtained.A CMOS-compatible p-TFET was also designed to meet all the requirements for developing a SRAM cell.The parameters such as I on = 34.4µA/µm, SS avg = 51.78mV/dec, and f T = 123 GHz illustrate that NCDL-TFET is a notable candidate for high-performance applications such as designing SRAMs with lower power dissipation.

Figure 3 .
Figure 3.Comparison between the measured transfer characteristic of the doping-less TFET22 and the reproduced curve by our calibrated simulation setup.

Figure 4 .
Figure 4.The energy bands diagram of NCDL-TFET along (a) A-B cutline and (b) C-D cutline.Impact of cladding layers doping concentration on the energy bands diagram of NCDL-TFET along the E-F cutline in (c) off-state and (d) on-state.

Figure 5 .
Figure 5. (a) Electron BTBT tunneling rate, and (b) electron current density contour maps at V GS = 0.7 V and V DS = 0.7 V.

Figure 6 .
Figure 6.Impact of cladding layers doping concentration on (a) transfer characteristic, (b) V th , V off , and I on , (c) transconductance, (d) cut-off frequency and (e) transit time of vertical NCDL-TFET.

Figure 7 .Figure 8 .Figure 9 .
Figure 7. Impact of channel thickness on (a) transfer characteristic, and (b) I on /I off , and SS min of vertical NCDL-TFET.

Table 1 .
Default values of the proposed TFET parameters.