The understanding of the impact of efficiently optimized underlap length on analog/RF performance parameters of GNR-FETs

The aim of this study is to examine the analog/RF performance characteristics of graphene nanoribbon (GNR) field-effect transistors (FETs) using a novel technique called underlap engineering. The study employs self-consistent atomistic simulations and the non-equilibrium Green's function (NEGF) formalism. Initially, the optimal underlap length for the GNR-FET by device has been determined evaluating the ON-current (ION) to OFF-current (IOFF) ratio, which is a critical parameter for digital applications. Subsequently, the impact of underlap engineering on analog/RF performance metrics has been analyzed and conducting a comprehensive trade-off analysis considering parameters such as intrinsic-gain, transistor efficiency, and device cut-off frequency. The results demonstrate that the device incorporating the underlap mechanism exhibits superior performance in terms of the ION/IOFF ratio, transconductance generation factor (TGF), output resistance (r0), intrinsic gain (gmr0), gain frequency product (GFP), and gain transfer frequency product (GTFP). However, the device without the underlap effect demonstrates the highest transconductance (gm) and cut-off frequency (fT). Finally, a linearity analysis has been conducted to compare the optimized GNR-FET device with the conventional GNR-FET device without the underlap effect.

Gate Induced Drain Leakage (GIDL) 29 , resulting in reduced switching power and improved suitability for logic applications.However, the underlap between the gate and the source or drain leads to an increase in channel resistance, which diminishes the ON-current and adversely affects device performance.To address this issue, an asymmetric underlap structure, where the underlap is applied on the drain side, is preferred 30 .Despite these advancements, the existing methods for enhancing the analog/RF performance of FETs remain inadequate.As a result, recent studies have focused on improving the analog/RF performance of GNR-FETs.This motivates further investigation into the analog and RF performance characteristics of GNR-FETs with underlap structures.Notably, there is a lack of prior research examining the analog/RF performance behavior of GNR-FETs employing the asymmetric underlap mechanism.
This research study focuses on examining the impact of underlap engineering on analog/RF parameters in GNR-FETs for low-power applications.To achieve this objective, the non-equilibrium Green's function (NEGF) methodology is employed to investigate the figure-of-merits (FOMs) related to analog and RF performance in GNR-FET devices with varying underlap lengths.Key parameters such as the gain frequency product (GFP) and gain transfer frequency product (GTFP) are analyzed, as they are crucial for circuit design and high-speed switching applications.The findings of this study can serve as a valuable resource for researchers involved in the design of novel GNR-FETs that exhibit superior performance compared to conventional FETs.Moreover, it is expected that this research will inspire further exploration of the application potential of GNR-FETs in diverse multidimensional contexts.
Device structure and simulation methodology., where m 0 represents the free mass of an electron, are essential for achieving optimal performance.The top and bottom gate oxide layers are composed of HfO 2 .We vary the underlap length from 0-nm to 10-nm, incrementing by 2-nm.The source and drain regions are doped with n-type dopants, while the underlap and channel length (L G = 8 nm) 26 are intrinsic regions.The simulations are conducted with a fixed drain-to-source voltage (V DS ) at a temperature of 300 K.The parameters used in the device simulation are presented in Table 1.
To accomplish the objective, the NanoTCAD ViDES atomistic device simulator perform all simulations within the non-equilibrium Green's function (NEGF) framework 34 .The tight-binding approximation is used to describe the interactions between individual carbon atoms in a graphene nanoribbon (GNR) at an atomic level.These interactions specifically involve the C-C atoms and are limited to the nearest neighboring atoms.In the NEGF approach, first-of-all, an appropriate Hamiltonian matrix for the channel is taken into account.The simulation employed a 2-band Hamiltonian, expressed as follows 35,36 : the parameters E A and E B represent the energy levels at the top of the valence band and the bottom of the conduction band, respectively.These can be expressed as E B -E A = E G , where E G is the bandgap.Here, only one atomic orbital and the primitive unit cell comprises only one atom is considered, which leads to the formation of a single energy band.In this simulation, the in-plane hopping parameter, denoted as t, has a value of 2.7 eV 31 .
After defining the Hamiltonian matrix, Green's function is calculated as Ref. 37 : which is examined by referencing earlier work 38 .After performing the Green's function calculation, the Schrödinger equation is solved with an open boundary condition to obtain the electron and hole concentrations.Subsequently, the electron density is calculated using Newton-Raphson iteration method.Ultimately, the Landauer formula 37 is employed to compute the drain current (I D ).In Green's function equation, E, I, H, D and S represent energy, identity matrix, material Hamiltonian, and self-energy matrix at drain and source terminals, respectively.

Results and discussion
To begin the analysis, the current simulator is calibrated to correspond to the device structure presented in Ref. 39 .Figure 2 demonstrates that obtained simulations are in good agreement with previous research findings.
Once the correctness of the simulation with the above-described methodology has been established, an underlap is introduced in the body of the GNR-FET at the drain end to assess the impact of Asymmetric underlap (UL) length on the performance of GNR-FET devices.It is important to clarify that whenever UL is mentioned unless explicitly stated otherwise, it refers to the default Asymmetric UL of drain extension.
Optimization of underlap length.After confirming the accuracy, the impact of UL engineering on the transfer characteristics of GNR-FETs is examined.Figure 3 depicts the impact of UL length in the I D as a function of gate-to-source voltage (V GS ) of GNR-FETs in which the underlap length is varied from 0-nm to 10-nm with a step-size of 2-nm to get an optimized underlap state.The optimized state of the device is achieved by utilizing digital performance FOM, ON-current to OFF-current ratio.The I D values for the ON-state and OFF-state are examined at V DS = 0.3 V, V GS = 0.8 V, and It is observed from Fig. 4 that a significant amount of DIBL is present in the device with low underlap length, which implies a larger I OFF .When the underlap length increases, the DIBL decreases, resulting in a reduced I OFF without considerably lowering I ON .As a result, the I ON /I OFF ratio increases.The Underlap length eventually rises (1) (3) www.nature.com/scientificreports/ to a level where DIBL is no longer important.As a result, a small change in the I OFF is seen as underlap increases.However, raising the underlap raises the total resistance of the channel, which dramatically reduces the I ON after some point.As a result, I ON /I OFF begins to decline.Figure 5 depicts the surface potential plot of the simulated structure for various underlap lengths.It is observed from Fig. 5 that the induced inversion charge of the device rises as the underlap length of the device increases.As a result, the potential barrier in the UL region is enhanced.Following the observation of the surface potential curve, the effects of UL engineering on the transmission window for carrier transmission are investigated.Figure 6 depicts the transmission probability variation with   www.nature.com/scientificreports/energy, and it is observed that with the increase of UL length of the device, the transmission probability curve decreases, which results smaller drain current 39 .
From the above graphs and discussion, it is clear that the optimal underlap point is achieved at a UL length of 6-nm.Henceforth, an UL length of up to 6-nm is elected for further analysis and compare the results with a conventional GNR-FET device having zero underlap gap between the gate and drain regions.
Analog performance.The analog performance FOMs of the GNR-FET device are discussed in this section.The parameters investigated and analyzed here are as follows: the transconductance (g m ), transconductance generation factor (TGF), output resistance (r 0 ), and intrinsic gain (A V ).The parameters g m and TGF are expressed as follows: Figure 7 depicts the changes in g m concerning V GS , where it is observed that initially g m increases rapidly with gate voltage and finally appears to peak and then decreases.This rising and falling tendency in g m is due to the I D variation of the device with V GS .It is evident that the device with UL = 6-nm has a lower g m .It is because of degraded mobility in the channel due to increased channel resistance with UL engineering.The TGF is another crucial factor for analog applications.The concept of TGF refers to the effective utilization of drain current in achieving a desirable g m value.A higher TGF value suggests that the device is well-suited for low-power amplifier designs.Figure 7 depicts the variation of TGF with respect to V GS .It is observed from Fig. 7 that the TGF curve improves with UL structure at low V GS , although there is no substantial improvement with high V GS .Moreover,  the maximum value of TGF is obtained with the UL = 6-nm structure due to the lower I D in the GNR-FET with the UL effect.The intrinsic gain (A V ) is another significant FOM for analog operation.The A V should be as high as possible for optimal analog performance.The A V can be defined and calculated as follows: It is clear from the above equation that A V depends on the device's r 0 and g m .Thus, understanding the variation of r 0 is required before studying A V .It is observed from Fig. 8 that r 0 increases with UL engineering.This is due to the enlargement in channel resistance with underlap length.As the channel resistance increases, the conductivity of the channel decreases.As a result, r 0 increases with underlap length.
Figure 8 depicts the effect of underlap engineering on A V .It is evident from Fig. 8 that initially A V increases, eventually appears at peak value, and then decreases.The initial rise in A V can be attributed to the dominance of g m over r 0 .As the gate voltage increases, the value of g m approaches a constant value for shorter period of V GS , after which it decreases, while r 0 keeps decreasing, leading to a Bell-shaped A V curve.

RF performance.
To evaluate the effectiveness and feasibility of underlap on RF applications of devices, two essential RF FOMs; gate capacitance (C G ), and cut-off frequency (f T ) are analyzed in this section.
The C G of a device is an essential FOM for with RF applications.The C G of a device can be calculated as the ratio between the change in charge carrier concentration and the change in V GS .The variation of C G with respect to V GS and underlap effect is shown in Fig. 9, and it is observed that with the introduction of underlap effect, the gate capacitance of the device rises.The peak value of C G without UL mechanism is observed as 1.46 fF, whereas, with UL engineering of 6-nm, the maximum value of capacitance is 2.25 fF.
One of the crucial factors in determining a device's RF performance is the cut-off frequency (f T ).The frequency at which the current gain is equal to 0-dB is known as f T .The f T is calculated by the following expression:  www.nature.com/scientificreports/ Figure 10 shows the f T variation with I D for GNR-FET devices.According to Eq. ( 7), the f T depends on g m to C G ratio; And the GNR-FETs with UL structure has a smaller value of g m and a larger value of C G .Hence, it is obvious that f T will decrease in devices with UL mechanism compared to a device with no underlap effect.
In the design of analog circuits, achieving a balance between device efficiency, bandwidth, and intrinsic gain is a critical factor.Trade-off analysis can be utilized to identify the optimal operating point by examining several metrics, including the gain frequency product (GFP) and gain transconductance frequency product (GTFP).GFP, which is calculated as GFP = (g m r 0 ) f T , is a significant property for operational amplifiers employed in high-frequency applications 40 .
Figure 11 depicts GFP variation with V GS .The underlap effect produces the maximum value of GFP, while at low and high V GS , the GFP with no underlap effect has a higher value.However, to determine the best operating point for analog circuits, it is more critical to consider how device efficiency, inherent gain, and frequency can be traded off.As a result, GTFP is evaluated.A higher GTFP value enables the circuit designer to adjust gain, transconductance, and cut-off frequency to achieve the optimal operating region 41 .The GTFP is defined as the product of GFP and TGF. Figure 12 shows the variation of GTFP with V GS .It is observed that the GTFP value is highest for the GNR-FET device with underlap engineering, due to its higher transistor efficiency and output resistance.

Impact of symmetric underlap length.
In this section, we analyze the impact of symmetric underlap length on the transfer characteristics of the device and compare it with the optimized asymmetric Source/Drain  www.nature.com/scientificreports/extension.Specifically, we consider the optimized asymmetric underlap length as UL = 6-nm and a symmetric underlap of 6-nm for our comparison.Figure 13 illustrates the impact of asymmetric underlap (UL) length and symmetric underlap (SUL) length on the I D concerning the V GS of GNR-FETs.It is evident from Fig. 13 that the drive current decreases, while the off-current increases considerably in SUL 6-nm compared to UL 6-nm underlap.This is due to the significant influence of series resistance in the region of operation.In a SUL DG FET, there exists a swapping between   on-current and fringing capacitance.While utilizing the underlap engineering can decrease parasitic capacitance, it also results in higher source/drain resistances 30 .To make it viable for system-on-chip applications, where analog and digital circuits coexist on the same integrated circuit, efforts should be directed towards identifying the optimized device with the highest on-off current ratio.

Linearity analysis.
Linearity is a crucial requirement in RF applications 42 .To achieve a distortion-free output signal with minimal intermodulation and higher-order harmonics, MOS devices with high linearity are essential.Non-linearity in this context is typically associated with higher-order transconductance, representing higher-order derivatives of a transistor's transfer characteristics.In this study, several metrics, namely g m2 , g m3 , VIP2 and IIP3 43 are used to assess RF linearity of an asymmetric underlap length near the channel-drain junction, and compare it with the device without underlap.
We will begin by focusing on the impact of higher-order transconductance FOMs, specifically g m2 and g m3 , which can introduce non-linearity by interfering with the fundamental frequency.To address this non-linearity, g m3 is considered the dominant parameter compared to g m2 .The even-order harmonics in circuits can be effectively mitigated through balanced topologies, making the impact of g m2 manageable in maintaining high linearity.On the contrary, g m3 proves to be highly unpredictable, thus imposing lower limits on distortion.Consequently, minimizing the amplitudes of g m2 and g m3 to the greatest extent possible is crucial to achieving high linearity in RF applications.
The transconductance of the second order (g m2 ) and the transconductance of the third order (g m3 ).The g m2 and g m3 are determined as Ref. 44 : If a device has a greater peak value of g mn at a lower V GS compared to another device, it is considered to have better linearity 45 .Figure 14 displays the variation of g m2 , while Fig. 15 depicts the variation of g m3 with V GS for GNR-FET devices under study.It is interesting to note from Figs. 14 and 15 that conventional and UL GNR-FET devices have first peak values of g m2 and g m3 at the same V GS .Therefore, in order to determine the device with the best linearity among those under consideration, further investigation of linearity parameters such as VIP2 and IIP3 is required.
VIP2 is utilized to evaluate distortion characteristics based on dc parameters.Improved linearity performance and reduced distortion operation are attained with higher values of VIP2 and IIP3.The IIP3 represents the input power level at which extrapolation results in the first-order power being equal to the third-order power.Having a high IIP3 value allows for enhanced linearity performance operation.: where R S represents source resistance.For most RF applications, R S = 50 Ω is considered.
The variation of VIP2 with V GS is shown in Fig. 16.It can be observed from the figure that the device without underlap architecture exhibits a higher VIP2 value when compared to the UL design.Figure 17 shows the (8)

Conclusion
In this study, the optimization of the underlap length and the comparative analysis of analog and RF FOMs for the GNR-FET device is performed.The study examines the impact of underlap structure on the drain side of the GNR channel in analog and RF applications, comparing it to an ideal device without underlap in the GNR channel.The optimized device with underlap structure demonstrates notable enhancements, including a 102% increase in I ON /I OFF ratio and a 12.33% decrease in DIBL compared to the conventional GNR-FET device without underlap.Similarly, GNR-FETs with underlap structures exhibit a 38.49% increase in TGF and a 54.32% increase in intrinsic gain compared to conventional GNR-FET devices.The results also highlight significant changes in RF performance metrics, with a 53.41% increase in gate capacitance, a 11.48% increase in GFP, and an 22.78% increase in GTFP.However, the cut-off frequency of the GNR-FETs is reduced by 43.3% compared to the ideal GNR-FET device.Therefore, underlap engineering in GNR-FETs is particularly advantageous for analog circuit applications where high transistor efficiency (TGF), gain, GFP, and GTFP are of primary importance.This approach enables a balance of device efficiency, gain and frequency, making it well-suited for medium to highfrequency applications.However, for RF performance and stability, the device without underlap is preferable.Consequently, the discussed parameters exhibit high sensitivity to the underlap structure of GNR-FETs, and the underlap mechanism can be utilized to regulate the performance of double-gate GNR-FETs based on specific application requirements.
Figure 1a and b illustrate the cross-sectional view and top view, respectively, of the simulated 12-armchair double-gated (DG) GNR-FET with underlap engineering.The channel and the source/drain are formed by a 1.37 nm-wide 2D graphene sheet.The lattice constant in GNR is 2.46 Å, and the carbon-carbon (C-C) bond length (d) is 1.42 Å.Our focus on 12-armchair GNRs stems from previous research suggesting that a bandgap of 0.6 eV and an effective mass of 0.064 m 0 31-33

Figure 1 .
Figure 1.Schematic of GNR-FET: (a) Cross-sectional view (b) Top view (The image only shows the surface of GNR).

Figure 2 .
Figure 2. Calibration of I D -V GS characteristics of the simulator and reported 39 data.

Figure 3 .
Figure 3. Transfer characteristics of GNR-FETs with various underlap length at V DS = 0.3 V.

Figure 4 .
Figure 4. Variation of DIBL and current ON/OFF ratio for different underlap length.

Figure 5 .
Figure 5. Surface potential plot of the device at V GS = 0.8 V.

Figure 6 .
Figure 6.Transmission probability variation with energy at V GS = 0.8 V.

( 6 )Figure 7 .
Figure 7. Variation of g m and TGF with V GS at V DS = 0.3 V.

Figure 8 .
Figure 8. Plot of r 0 and A V with V GS at V DS = 0.3 V.

Figure 10 .
Figure 10.Cut-off frequency (f T ) with varying I D .

Figure 11 .
Figure 11.Plot of GFP with V GS .

Figure 13 .
Figure 13.I D -V GS of GNR-FETs with asymmetric and symmetric underlap length of 6-nm at V DS = 0.3 V.

Figure 14 .
Figure 14.Variation of g m2 with V GS .

Figure 15 .
Figure 15.Variation of g m3 with V GS .

Table 1 .
Parameters of the GNR-FET structure.