Photonic synaptic transistors with new electron trapping layer for high performance and ultra-low power consumption

Photonic synaptic transistors are being investigated for their potential applications in neuromorphic computing and artificial vision systems. Recently, a method for establishing a synaptic effect by preventing the recombination of electron–hole pairs by forming an energy barrier with a double-layer consisting of a channel and a light absorption layer has shown effective results. We report a triple-layer device created by coating a novel electron-trapping layer between the light-absorption layer and the gate-insulating layer. Compared to the conventional double-layer photonic synaptic structure, our triple-layer device significantly reduces the recombination rate, resulting in improved performance in terms of the output photocurrent and memory characteristics. Furthermore, our photonic synaptic transistor possesses excellent synaptic properties, such as paired-pulse facilitation (PPF), short-term potentiation (STP), and long-term potentiation (LTP), and demonstrates a good response to a low operating voltage of − 0.1 mV. The low power consumption experiment shows a very low energy consumption of 0.01375 fJ per spike. These findings suggest a way to improve the performance of future neuromorphic devices and artificial vision systems.

attract attention for optical devices such as solar cells 21 and photodetectors 22 .However, they are very vulnerable to moisture, and their photoelectric efficiency decreases significantly when exposed to the atmosphere for a long time 23 .In this respect, CsPbBr 3 made of inorganic materials has better stability than other organic-inorganic perovskites 24 .
Most light-driven organic synaptic devices consist of a double layer composed of a channel and a light absorption layer.When the light-absorption layer absorbs photons and generates an electron-hole pair, each channel and light-absorption layer is dominated by holes and electrons, respectively.The energy barrier caused by the different energy levels of each layer prevents the recombination of electrons and holes, resulting in synaptic phenomena where the drain current flows after light illumination is turned off 12,14 .However, most double-layer devices perform poorly in terms of the output current and "energy consumption per spike, " which are important parameters for measuring the performance of synaptic devices.
In this work, we dramatically improved the photoreactivity and energy consumption characteristics compared to those of the double-layered device by implementing a triple-layer device in which a new electron trapping layer (NETL) is adopted.The triple-layer device with a NETL lowers the electron-hole recombination rate compared to a double-layer device.This improvement enhances the carrier lifetime, which, in turn, contributes to an increase in channel conductivity.
We used 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene, or simply TIPS), a p-type organic semiconductor material, as the channel layer and CsPbBr 3 as the light absorption layer 12 .SnO 2 was utilized as a NETL because it is simple to fabricate, has a valence band level that can create an energy barrier to trap electrons in conjunction with CsPbBr 3 , and provides a smooth thin-film surface 25,26 .
This paper presents a method capable of detecting very weak light.The approach boasts a higher photosensitivity than those previously reported for various photonic synaptic perovskite systems.
Device fabrication.Heavily doped n-type silicon with 100 nm SiO 2 was used as the substrate.To prepare a clean substrate, ultrasonication was performed on the substrate for 10 min in the order of acetone, isopropyl alcohol, and deionized water.O 2 plasma was applied to the substrate for 5 min.Next, the prepared SnO 2 colloidal solution was dropped onto the substrate and spin-coated at 3000 rpm for 30 s, followed by annealing at 150 °C for 30 min.Next, the CsPbBr 3 solution was spin-coated onto SnO 2 at 4000 rpm for 60 s.The sample was placed in a vacuum pump to remove the solvent 12 .Then, the TIPS solution was spin-coated onto the perovskite layer at 1000 rpm for 10 s and annealed at 100 °C for 10 min.Finally, 50 nm of Au was thermally evaporated to form source and drain electrodes with a channel width of 1000 μm and a length of 50 μm.A simplified pictorial illustration of this fabrication process is shown in Fig. 1.

Characterization and measurements.
Electrical measurements were conducted in an ambient atmosphere using a Keithley 4200-SCS semiconductor parameter analyzer to gauge the synaptic performance of the device.For the light-dependent experiments, measurements were performed under dark conditions to avoid ambient light interference.UV-vis absorption measurements were performed using a JASCO V-750 spectrophotometer.The optical microscopy image of the device was observed using an Olympus BX51 microscope, and the nano images were observed using a JSM-7100F FE-SEM.

Result and discussion
Device structure and working principles of photonic synaptic transistors.Understanding the biological synaptic mechanisms, illustrated on the left side of Fig. 2a, is helpful in developing a neuromorphic system.Synapses are links between neurons that exchange information from the presynaptic to the postsynaptic neuron 13,27 .In response to external stimuli, neurotransmitters bind to the receptors of postsynaptic neurons by creating postsynaptic currents.The right side of Fig. 2a shows the proposed photonic synaptic device that mimics this biological process.The external input is defined as a light spike, and the increased drain current is defined as an excitatory postsynaptic current (EPSC), which is crucial for the acquisition, transmission, and storage of data in synaptic devices 28 .
Energy band diagrams are shown in Fig. 2b and c to describe how photonic synaptic devices function in double and triple layers, respectively, where stairwise energy barriers are formed between the layers.Electron-hole pairs are generated in the CsPbBr 3 perovskite when light illuminates the photonic synaptic transistor.In the double-layer device shown in Fig. 2b, the holes pass to the TIPS layer owing to the built-in potential bias 12 .However, electrons cannot cross easily owing to the barrier generated by the conduction band (CB) of CsPbBr 3 with the lowest unoccupied molecular orbital (LUMO) level of the TIPS.Therefore, even if the light is off, because electrons are trapped in CsPbBr 3 , recombination with holes is prevented, and the current continues to flow.However, in the double-layer structure, the barrier is not large enough to prevent recombination for a long time, so the electrons trapped in CsPbBr 3 recombine with the holes quickly, and no channel current flows.Differing from the double-layer device, in the SnO 2 /CsPbBr 3 /TIPS triple-layer device, the photogenerated electrons are directed to the SnO 2 layer rather than the CsPbBr 3 layer.Meanwhile, the holes migrate to the TIPS, similar to the double-layer structure.In this process, the physical distance and energy barrier between electrons and holes heighten compared to the double-layer device.This increase in distance and energy barrier is analogous to the use of electron and hole transport layers in solar cell research 29 .Therefore, owing to a diminished recombination rate in the triple-layer structure compared to the double-layer one, the number of holes contributing to the channel and the carrier lifetime increases.Using this energy-band engineering, the triple-layer structures exhibit improved optical responsiveness.
A cross-section of the fabricated triple-layer synaptic transistor is shown in Fig. 3a.The device was fabricated using a solution process, except for the gold electrode.First, SnO 2 was spin-coated onto the Si/SiO 2 substrate.Subsequently, a CsPbBr 3 solution, prepared by mixing CsBr and PbBr 2 at a 1:1 molar ratio, was spin-coated on top of SnO 2 , yielding a CsPbBr 3 layer with a thickness of approximately 60 nm.The thickness was judiciously chosen to achieve an optimal balance between light absorption, charge carrier transport, and compatibility with device scaling.After the CsPbBr 3 layer deposition, TIPS was spin coated and thermal deposition of source/ drain electrodes followed.As shown on the right side of Fig. 3a, SnO 2 -coated SiO 2 shows a very homogeneous morphology 25,26 .In contrast, CsPbBr 3 perovskite crystals manifest dispersed island-shaped grains.A structure with fewer grain boundaries is advantageous for preventing ion migration, causing a gate-field screening effect in the perovskite 30 as ion immigration occurs at the grain boundary rather than at the grain.Furthermore, perovskite crystals react sensitively to weak light 12 .Further details about the fabrication process are provided in the Experimental section.Figure 3b and c show an image of the fabricated synaptic transistor.The channel length is 50 μm, and the width is 1000 μm. Figure 3d shows the UV-vis spectra of SnO 2 , TIPS, CsPbBr 3 , CsPbBr 3 /TIPS, and SnO 2 / CsPbBr 3 /TIPS films.The absorption in SnO 2 is extremely low compared to the other films; therefore, even if SnO 2 is added to the CsPbBr 3 /TIPS film, there is no significant change in the peak value and light absorption 16 .The peak values of the CsPbBr 3 /TIPS and SnO 2 /CsPbBr 3 /TIPS films are similar to those of the TIPS film at 488 nm, indicating that TIPS determines the peak values.Because a high photocurrent gain can be obtained using the light of the wavelength closest to the peak 20 , for the light illumination experiment, we fixed the wavelength to 450 nm using an LED to give impulsive spikes on the device.Synaptic characteristics and performances of photonic synaptic transistors.Figure 4a and b show the transfer curves of CsPbBr 3 /TIPS and SnO 2 /CsPbBr 3 /TIPS photonic synaptic transistors, respectively, measured at a drain voltage (V d ) of − 40 V.When light is applied to each photonic synaptic transistor, the curve moves in the positive direction owing to the influence of the photo-generated electron-hole pairs.The curve moves to the right as it receives more intense light 12 , showing that the stronger the light, the higher the current obtained at the same gate voltage.When measuring the memory window, which represents the change in threshold voltage upon light illumination compared to the dark condition, the double-layer device at a defined light intensity (I op ) of 0.635 μW/cm 2 demonstrated a value of 38.9 V.This value is relatively high, particularly when considered in the context of the comparatively weak light intensity of 0.635 μW/cm 2 employed in the experiments.However, the triple-layer device showed a much-improved memory window of 51.3 V.This is because, as The synaptic characteristics of photonic synaptic transistors can be evaluated using the transient response of the current to light illumination 16 .Figure 5a shows the response currents in the double-and triple-layer devices.The time (t light ) and intensity of the illuminated light were 1 s and 84 μW/cm 2 , respectively, at V d = − 1 V.The gate voltage (V g ) was fixed at 0 V.The current increment (ΔEPSC) is depicted in the graph instead of the raw current value because the ground levels of the two transistors are different: 0.035 nA for the double-layer and 0.547 nA for the triple-layer.EPSC peaks appear in both the double-layer and triple-layer transistors during the period in which light is applied, but ΔEPSC is 1.309 nA in the triple-layer device, which is 2.16 times larger than 0.605 nA in the double-layer device.These results show that the increased energy barrier in the triple-layer device effectively inhibits the recombination of electrons and holes.
When a light spike is continuously applied to the photonic synaptic transistor, the photocurrent generated by the second spike (A 2 in Fig. 5b and c) exceeds that generated by the first spike (A 1 in Fig. 5b and c).This phenomenon is known as paired-pulse facilitation (PPF) 13,31 and is defined by Eq. ( 1): This phenomenon results from synaptic plasticity, which further increases the current if the second spike comes before the electrons and holes generated by the first spike are completely recombined.The PPF experiment was conducted at t light = 1 s and I op = 84 μW/cm 2 intensity, and the time interval (Δt) between the two spikes was varied from 1 to 3 s. Figure 5b and c show the EPSC graphs measured at Δt = 1 s, showing higher EPSCs in the triple-layer device (Fig. 5c) than in the double-layer device (Fig. 5b). Figure 5d shows the PPF index measured at various Δt values for the double-and triple-layer devices.In both cases, the PPF ratio decreases rapidly as Δt increases, then gradually converges.For the double-layer device, the PPF decays from 146.06 to 107.25%, whereas the triple-layer device decays from 176.35 to 114.39%.The triple-layer device shows a higher PPF index at Δt than the double-layer device.Owing to the larger energy barrier of the triple-layer device, the hole remains in the TIPS for a longer time before recombination with the electron, and thus a greater number of carriers remain in the channel until the second light arrives.
Analogous to how repeated information can be better memorized in the human brain, the transition from short-term potentiation (STP) to long-term potentiation (LTP) when a longer and stronger stimulus is applied is also an important characteristic of synaptic devices 10 .In Fig. 6a and b, changes in the EPSC can be observed according to the spike widths of light.The light intensity was 84 μW/cm 2 in this experiment.Carriers are continuously created with continuous light input, resulting in a higher current.In Fig. 6d and e, the change in EPSC is observed while changing the number of consecutive light spikes from 1 to 10 under the conditions of (1) PPF = (A 2 /A 1 ) × 100 % www.nature.com/scientificreports/t light = 1 s, Δt = 1 s, and I op = 84 μW/cm 2 .Similar to the previous experiment, the higher the number of spikes, the higher the peak current.Finally, Fig. 6g and h show the results of experiments applied to double-and triple-layer photosynaptic transistors for 1 s while varying the light intensity.A higher EPSC can be obtained because more electron-hole pairs are generated as the light intensity increases.In addition, owing to the increased energy barrier, experiments using triple-layer devices in Fig. 6b, e, and h show higher photoreactivity than results from double-layer devices in Fig. 6a, d, and g.The trend of change in the peak value of each experiment can be compared in Fig. 6c, f and i, where it can be seen that the slope of the curve becomes flatter as the stimulus (spike widths, number of light spikes, and light intensity) applied to the device increases.This is because the strong stimulus causes the electrons in CsPbBr 3 in the photon absorption layer to reach a high density, and the new photogenerated holes directly recombine with the electrons before moving into the TIPS layer 19 .From the results shown in Fig. 6i, it is evident that the triple-layer device exhibits a response rate that is more than twice as high as that under both low and high light intensities.This increased response is predominantly attributed to the energy band mechanism intrinsic to the triple-layer structure, which effectively lowers the recombination rate of electrons and holes.As a result, this implies a significantly larger number of residual channel carriers, or holes, available to contribute to the channel current.One peculiar result of these experiments is that the triple-layer device shows a relatively steady increase in EPSC with a lower tendency toward saturation than the double-layer device.This is because, as electrons generated in the triple-layer device move to the SnO 2 layer, the recombination of electrons and holes in the CsPbBr 3 layer is reduced, and the lifetime of the holes is increased.Owing to this increased hole lifetime, the maximum photocurrent that can be reached is higher than that of the double-layer device.
In the transistor with the added NETL, both the increment in the EPSC and the effect of prolonging the retention time were observed.Figure 7a shows the decay of the EPSC in both double-layer and triple-layer devices under the STP condition (single spike).Because the peak EPSC values of the two transistors are different, each peak value is normalized to 1. Fifty seconds after the light is turned off, the EPSC of the double-layer device retains 8.505% of the peak value, while 15.331% of the peak value is retained in the triple-layer device.This shows that the transistor with the SnO 2 layer has better retention characteristics than the double-layer device under the same operating voltage and light conditions.The LTP results were obtained by applying 20 consecutive spikes (Fig. 7b).For the double-layer device, the EPSC decreases to 17.096% of the peak current value 50 s after the light is turned off, but in the case of the triple-layer device, it decreases only to 24.567%.This result also indicates that the triple-layer device has better retention characteristics than the double-layer device, and that the retention time is longer in the LTP condition than in the STP condition.The graph in Fig. 7c compares the memory characteristics for the double-and triple-layer devices at 50 s after the light is turned off.Overall, our device's relatively high EPSC and long retention time demonstrate higher performance under the same voltage and light conditions and also provide a significant advantage over the double-layer for long-term image memory in vision systems.
To investigate the performance under low power conditions 32 , the device operation was measured while lowering the operating voltage.Figure 8a and b present ΔEPSC obtained by lowering the operating voltage from − 0.1 to − 0.001 V under the condition of t light = 1 s and I op = 42 μW/cm 2 .Although the current rapidly decreases as the operating voltage decreases, both the double-and triple-layer devices respond to light spikes in this voltage range.To test the consumption limit of our device, we prepared an extreme condition of very low operating voltage, low spike width, and low intensity of light (V d = − 0.1 mV, t light = 0.01 s, I op = 0.17 μW/cm 2 ).Under these conditions, the double-layer device cannot derive a distinguishable peak value, and only noise can be observed (Fig. 8c).Conversely, Fig. 8d shows that the triple-layer device undergoes a photoreaction, indicating that more holes survive in the channel in the triple-layer device than in the double-layer device.The energy consumption of this single spike is calculated using the following formula: [33][34][35] Our synaptic device has a very low energy consumption of 0.01375 fJ, which is about 1000 times lower than the approximately 10 fJ occurring in the human brain 13 .A comparison with recently published results is presented in Table 1.

Conclusions
In conclusion, we achieved a high-performance synaptic effect in a triple-layer device by integrating the widely studied CsPbBr 3 and introducing the NETL material SnO 2 .Our innovative triple-layer configuration, different from the conventional double-layer where electrons were trapped in the perovskite, allowed the confinement of electrons in the NETL situated beneath the perovskite layer.This arrangement formed a higher energy barrier, reducing the electron-hole recombination rate and leading to a marked enhancement in the EPSC.The device demonstrated various synaptic effects such as PPF, STP, and LTP, and showed extremely low energy consumption in the power consumption test, marking its potential for applications demanding energy efficiency.The practicality of mass-production through straightforward and cost-effective solution processes like spin-coating further increases its value.While our device exhibited reasonable stability, showing photoresponsivity for about a week, longer-term stability was compromised.Future work will aim to improve this aspect, potentially through the implementation of capping materials or novel packaging technologies.Moving forward, we acknowledge the ongoing research towards the development of materials with superior photoreactivity and less toxicity for optimization of these devices.Our work contributes significantly to the construction of networks essential for future neuromorphic computing and artificial vision systems.It lays a promising foundation for potential applications including small-scale devices, mobile applications, and complex visual recognition tasks in areas like robotic systems, further substantiating the potential of our findings 36 .
(2) E per spike = V d • I peak • t light

Figure 1 .
Figure 1.Schematic representation of the fabrication process of the triple-layer photonic synaptic transistor.The process begins with SnO 2 spin coating, followed by consecutive spin coating of CsPbBr 3 and TIPS, and finally Au electrode patterning.

Figure 4 .
Figure 4. (a) Transfer curves under dark and various illumination conditions for double-layer and (b) triplelayer devices.

Figure 5 .
Figure 5. (a) Depiction of synaptic characteristics for both double-layer and triple-layer devices.(b) Reaction of EPSC to two successive light spikes in the double-layer device.(c) Reaction of EPSC to two successive light spikes in the triple-layer device.(d) Representation of PPF index as a function of spike interval (Δt) for both double-layer and triple-layer devices.

Figure 6 .
Figure 6.(a-b) ΔEPSC as a function of spike widths for double-layer and triple-layer devices, respectively.(c) Peak of ΔEPSC (ΔEPSCp) as a function of spike widths.(d-e) ΔEPSC when influenced by varying numbers of consecutive light spikes in double-layer and triple-layer devices, respectively.(f) ΔEPSCp as a function of spike number for double-layer and triple-layer devices.(g-h) ΔEPSC measurements at various light intensities for double-layer and triple-layer devices, respectively.(i) ΔEPSCp as a function of light intensity for double-layer and triple-layer devices.

Figure 7 .
Figure 7. Depiction of EPSC decay characteristics and memory attributes for double-layer and triple-layer devices: (a) EPSC decay after the application of a single light spike; (b) EPSC decay following 20 consecutive light spikes; (c) Comparison of memory characteristics recorded at 50 s after the light is turned off for both device types.

Table 1 .
Comparison of power consumption of the photonic synaptic transistors recently reported.