Spin–orbit torque flash analog-to-digital converter

Although analog-to-digital converters (ADCs) are critical components in mixed-signal integrated circuits (IC), their performance has not been improved significantly over the last decade. To achieve a radical improvement (compact, low power and reliable ADCs), spintronics can be considered as a proper candidate due to its compatibility with CMOS and wide applications in storage, neuromorphic computing, and so on. In this paper, a proof-of-concept of a 3-bit spin-CMOS Flash ADC using in-plane-anisotropy magnetic tunnel junctions (i-MTJs) with spin–orbit torque (SOT) switching mechanism is designed, fabricated and characterized. In this ADC, each MTJ plays the role of a comparator whose threshold is set by the engineering of the heavy metal (HM) width. Such an approach can reduce the ADC footprint. Monte-Carlo simulations based on the experimental measurements show the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. Moreover, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively.

quantizer to sense each MTJ resistance 20 . The difference in resistances of the adjacent HMs is compensated by adjusting the size of the transistor in the sensing circuit 21 . However, in the proposed solutions, increasing the complexity of the sensing circuit is the cost of mitigation issue of MR degradation.
In this paper, the proof-of-the-concept of implementing an ADC based on spintronic devices is investigated which provides design guidelines for future spin-CMOS ADCs. To this end, a spin-CMOS ADC is proposed, designed, and characterized in which SOT-based MTJ and its ISOT,crit act as a comparator and reference current (Iref) in conventional current-mode Flash ADCs, respectively. In spite of the proposed structures in literatures [18][19][20] , in this structure, in-plane anisotropy MTJs (i-MTJ)s are placed in parallel branches to mitigate the MR deduction and the complexity of the sensing circuit. The impact of the HM resistance on the MR is shown by comparing the measurement data extracted from the structure proposed in literature 19 with the approach presented in this paper. The measurement results show that the MR values of the proposed ADC are more than those of the structure in 19 which means the reading reliability can be improved in the proposed structure. The input current (Iin) is copied to each branch and in case Iin is higher than ISOT,crit of the MTJ, the MTJ will switch. Hence, ISOT,crit of each i-MTJ can behave like Iref in the current-mode CMOS Flash ADCs. All i-MTJs are set in the P-state and if Iin > ISOT,crit, the i-MTJ is switched to the AP-state. The width of the HM (wHM) is tuned so that the ISOT,crit of each MTJ is compatible with reference currents (Iref, 2Iref, 3Iref, ...) of the current-mode CMOS Flash ADC. Furthermore, Monte-Carlo simulation is performed to analyze the impact of the process variations/mismatch of the i-MTJs and transistors on the reference currents of ADC. To this end, a random variable with a Gaussian distribution for each i-MTJ is considered. The mean and standard deviation (σ) of the variable are defined by the measurement data of the i-MTJs. Moreover, the variations of the CMOS circuit (the current mirror of Iin) has been included to extract the ISOT,crit values.

Spin-CMOS ADC
The principle of the SOT switching mechanism in the FL of the SOT-based MTJ is shown in Fig.1 (a). In this structure, a charge current (ISOT) flows through the HM along the x-direction. The SHE in the HM creates a pure spin current in z-direction, which is magnetized along the y-direction. This pure spin current generates an STT, which can switch the FL magnetization at a critical spin current density ( , ), which is similar for all MTJs that are nominally identical. The conversion efficiency between the charge current density and the spin current density is described by the spin Hall angle . So, the (1) with the critical change current density ( , ), the electrons charge e, the electrons spin expressed by the reduced Planck's constant ℏ and the HM thickness t . Thus, the charge current required for switching is proportional to w , which makes tuning of the critical charge currents relatively easy in these devices.
The schematic of the current-mode Flash ADC which consists of the input, Iref, comparator, and thermometer code to binary (T2B) encoder blocks are depicted in Fig.1 (b). Flash ADCs are categorized into two groups: 1) voltage mode and 2) current mode.

Vout2
... Current-mode Flash ADCs have some advantages over voltage-mode ADCs, such as less power consumption and the ability to operate with smaller supply voltages 21 . The input block makes several copies from Iin, then the comparator block compares these copies with reference currents coming from Iref block. The outputs of the comparator block are encoded by the T2B encoder and binary data corresponding to the input signal is generated as the ADC output. Hence, in the n-bit current-mode CMOS Flash ADC, 2 n -1 copies of Iref with different weights (i.e., Iref0, 2Iref0, …, (2 n -1)Iref0) and Iin are required. The main idea of the proposed work is to replace the current mirror circuits needed for generating different copies of Iref as well as the comparator block by an SOT-based MTJ as shown in Fig.1 (b). Since Iref values are multiplications of Iref0, the size of transistors in the current mirror circuit will progressively increase. By replacing Iref and comparator blocks with an SOT-based MTJ, space and mismatch issues can be mitigated. As shown in Fig.1 (b), ISOT as an input current (Iin) flows through the HM from T2 to T3 and as mentioned before the SOT-based MTJ acts as a comparator; hence it compares the Iin with its ISOT,crit (behaves as the Iref block). To sense the MTJ resistance, a current (ISens) passes through the MTJ and a part of the HM from T1 to (T2/T3). The 3-bit spin-CMOS Flash ADC in two different designs called parallel and serial designs are shown in Fig.1 (c) and (d), respectively. In both, seven SOT-based MTJs are utilized to create an ADC with 3 bits of resolution. By engineering the wHM, ISOT,crits can be tuned so that by increasing wHM, the required current for switching the SOT-based MTJ will increase 25 . To this end, wHM of each MTJ should be properly designed to ensure that ISOT,crits for SOT-based MTJ1, SOT-based MTJ2, …, SOT-based MTJ 7 are equal with ISOT,crit, 2ISOT,crit, 3ISOT,crit, …, and 7ISOT,crit, respectively. In the serial design [18][19][20] , the SOT-based MTJs are put in series through HMs. As shown in Fig. 1(d), by using this design, the input block (shown in Fig. 1(b)) that consists of the Iin mirror branches can be removed. However, the HM resistance (depending on the MTJ position) degrades the MR and the reading reliability. For instance, if T2 ( Fig. 1(d)) is connected to the ground, the sensed resistance by ISens from T1,7 to T2 according to the equivalent resistive network of the SOT-based MTJ depicted in Fig. 1(b) that is RMTJ7 + 1/2 RHM7 + RHM6 + …+ RHM1. Therefore, the MR for SOT-based MTJ 1 is RMTJ7(AP)-RMTJ7(P)) / (RMTJ7(P) + 1/2RHM7 + RHM6 + … + RHM1) where, RMTJ(AP) and RMTJ(P) are the SOT-based MTJ resistance when SOT-based MTJ is in AP-state and P-state, respectively. Moreover, the different resistance seen from T1 of each MTJ leads to an increase in the complexity of the sensing circuit. To mitigate this issue, a parallel design, as shown in Fig. 1(c), is proposed in this paper. In this structure, SOT-based MTJs are detached and the HM resistance seen from T1 of each MTJ is almost equal if all MTJs are in the same states. However, Iin should be copied by current mirrors (the input block) and fed into each of the SOT-based MTJs. In both designs, the result of the comparison between Iin and ISOT,crit in each SOT-based MTJ is presented as a voltage signal (Vouti (1 ≤ i ≤ 7)). The T2B encoder block creates a 3-bit digital output (B0, B1, B2) based on Vouti. The detail of circuit design for sensing of SOT-based MTJ states and T2B are presented in 21 .

Results and discussion
The microscopic images of the serial and parallel designs are shown in Fig. 2 (a) and (b), respectively. Fig. 2(c) shows the MR versus minimum resistance (the resistance seen by ISens when the MTJ is in the P-state) for the two designs. In the serial design, T2 is connected to the ground. MR dependency with the position of the i-MTJ is observed for the serial design in which the MR difference between the lowest (belongs to MTJ7) and highest (for MTJ1) is around 47%. The MR for the MTJs with the width of 4.2 µm is the lowest as compared to the other MTJs because as mentioned before, the resistance seen from T1,7 to T2 is larger. In general, MR in the serial design is lower than that in the parallel design because of the large HM resistance. Moreover, the dependency of MR to i-MTJ position is much smaller in the parallel design because the resistance seen from T1 of each MTJ to the ground is RMTJ+RHM/2. The proof of concept of the implementation of a 3-bit Flash ADC based on the spintronic device can be investigated using the measured data from the characterization of the parallel configuration. To this end, the experimental setup of Fig. 3 (a) is utilized to characterize the MTJs. All MTJs are initially set to the AP state by applying an external DC magnetic field with an amplitude of 19 mT along +y. Afterwards, the external magnetic field is removed and ISOT is injected into the HM through T2. Subsequently, ISens (a DC current) with an amplitude of 100 µA is applied by a source-meter unit to measure the resistance between T1 and T3. This resistance, according to the equivalent resistive network of the SOT-based MTJ (Fig. 1 b) is RMTJ + 1/2 RHM. In this measurement, the samples have been reported that the amount of change in their resistance after switching (RMTJ(AP) -RMTJ(P)) and their MR are more than 68 Ω and 20%, respectively. Fig. 3 (b) depicts the MTJ resistance versus ISOT in absence of the external magnetic field for 7 SOT-based MTJs with different wHM. The positive (negative) current drives switching from P-state to APstate (AP-state to P-state). In this paper, P-state is considered as the initial state of the MTJ 3-bit spin-CMOS Flash ADC and the switching from P-state to AP-state occurs (during the conversion phase in the ADC [20]) at the critical charge current called ISOT,crit (P). During the reset phase in the ADC, SOT-based MTJs are switched back to their initial states at the critical charge current called ISOT,crit (AP), where the current direction is opposite of ISOT,crit (P). Moreover, as shown in the obtained R-I loops, the width of the R-I loop becomes larger by increasing the wHM, which means that, as mentioned in Eq. 1, by increasing wHM, the ISOT,crit (AP) and ISOT,crit (P) are rising.
The box plots of ISOT,crit (P) for seven categories are presented in Fig. 4 (a). Each category represents SOT-MTJs with the same size of wHM, in which wHM of category 1, 2, …, and 7 is 0.6 µm, 1.2 µm, …, and 4.2 µm, respectively. As shown in this figure, increasing wHM results in an increasing trend in ISOT,crit (P). σ of ISOT,crit for MTJ1, MTJ2, …, MTJ7 is 1.6 mA, 1.7 mA, 3.45 mA, 1.36 mA, 4.16 mA, 3.77 mA, 3.94 mA, respectively. The distribution of ISOT,crit (P) and HM resistance (RHM), which are subdivided by seven groups of different wHM , are depicted in Fig. 4(b). The trend of increasing ISOT,crit with RHM according to the equation of ISOT,crit (P) = const./ RHM (Eq.1 and RHM = const. / (tHM × wHM)) can be observed in this figure. As shown in Fig. 4(a) and (b), categories 1, 2 and 4 (wHMs are 0.6 µm, 1.2 µm and 2.4 µm) have the least variations while the variations of categories 3, 5, 6, and 7 are large and the distributions of these groups overlap with each other and other categories. Such large variations lead to nonlinearity, missing code and low accuracy issues in the ADC design based on the MTJs. Such random distributions are attributed to the variations in the wHM, tHM and MTJs. In particular, tHM is thin and the absolute variation is large that results in a large variation of the actual HM current density. Other way around, considering the nominal HM thickness this error results in a variation of the spin Hall angle. The MTJ variation is mainly due to the small size of the nano-pillars with dimensions similar to the grain sizes, which adds a random distribution. ISOT,crit(P) versus wHM is presented in Fig. 4(c) in which the square points and the solid line are the measurement data and a fitting line, respectively. In this figure, each point is the average data of each category of wHM that is extracted from Fig. 4(a). The fitting line to the data with 0.8243 of R-squared (R 2 ), represents a linear relation between ISOT,crit and wHM that is mentioned in Eq. 1. This linear dependency enables the linear ADC behavior. From the fitting line, we can determine  the characteristic critical current density of the device , = 0.6 × 10 , which describes how efficient the SOT current can switch the MTJs, which influences the precision of this ADC.
The differential nonlinearity (DNL) and integral nonlinearity (INL) characteristics for the proposed ADC are shown in Fig.5  (a). The maximum DNL and INL are 0.739 LSB (5 mA) and 0.7319 LSB, respectively. The simulation results are obtained by a behavioral model for MTJs in Verilog-A that is extracted from the measurement. In this model, ISOT,crit for each SOT-based MTJ is the mean value of each category that is extracted from Fig. 4 (c). The CMOS circuits (the current mirrors for Iin) are simulated using Cadence in TSMC 180nm technology. Monte-Carlo simulation is performed to evaluate the effects of the process variations/mismatch of the MTJs and CMOS circuits on the reference currents of ADC. The distributions of the reference currents shown in Fig. 5(b) are achieved by 300 simulation runs. Each plot includes the distributions of process variations and mismatch of the CMOS circuit of the Iin current mirror (Fig. 1(c)) and process variations of the related MTJ. For each MTJ, a behavioral model is considered that contains a variable with a Gaussian distribution. The values of mean and σ of the variable are extracted from Fig. 4 (a). ±2σ yield can be supported only if MTJ1, MTJ2, MTJ4 and MTJ7 are employed while histograms of MTJ3, MTJ5 and MTJ6 strongly overlap with other ISOT,crit distributions. Therefore, according to Fig. 4(b), the maximum available accuracy of the proposed ADC by such fabricated MTJs is 2 bits. The σ for MTJ1, MTJ2, …, MTJ7 are 1.5 mA, 1.6 mA, 3.3 mA, 1.3 mA, 4 mA, 3.7 mA, 3.8 mA, respectively. The values of σ are almost the same ones extracted from Fig. 4 (a) which means the process variation of MTJs is dominant as compared to the process variation and mismatch of the transistors.

Conclusion
In this paper, SOT-based MTJs are designed, fabricated, and characterized for the implementation of a 3-bit spin-CMOS Flash ADC. The linear relation between ISOT,crit and the width of HM was verified and the figure of merit of the SOT-based MTJ (JSOT,crit) is 0.6 × 10 Am -2 . Seven separated SOT-based MTJs with different width of HMs are employed. In this structure, MTJ and its ISOT,crit play the role of the comparators and Iref blocks in Flash ADC, respectively. Hence, the power-hungry comparators and the current mirrors that generate Irefs in current-mode Flash CMOS ADCs are eliminated. The current used for sensing the MTJ resistance, senses the HM resistance of only one MTJ in the path leading to significant improvement in MR and reading reliability. The maximum INL and DNL are in the range of 0.7319 LSB and 0.739 LSB, respectively. Furthermore, Monte-Carlo simulations are conducted for estimation of the ADC accuracy in the presence of the process variation/mismatch of the MTJ and CMOS transistors. The simulation results show the accuracy of the proposed ADC limits to 2 bits, which can be enhanced by improving the MTJ fabrication process in future.

Methods
An inverted MTJ stack with a 3-terminal geometry, similar to those used in previous works 22,[26][27] , was proposed. The MTJ consists in 15 W/ 1.4 CoFe40B20/ MgO/ 2.2 CoFe40B20/ 0.85 Ru/ 2.5 CoFe30/ 6 IrMn/ 5 Ru/ 140 Cu/ 30 Ru (thicknesses in nanometer) deposited on Si (100)/ 200nm thermal SiO2 by magnetron sputtering. The MgO thickness was targeted to have a resistance-area product (R×A) of 12 Ω.µm 2 , since that below 10 Ω.µm 2 a tunnel magnetoresistance (TMR) decrease is observed 28 . Through current-in-plane transport measurements, the stack exhibited an R×A of 14.3 Ω.µm 2 and 144% TMR. The tungsten in the stack was chosen as heavy metal due to the high spin hall angle reported in the β-phase 29 . However, this phase is only possible for W thicknesses of few nanometers (< 6 nm) 30 which is rather challenging for device fabrication since it reduces the stopping point margin for the pillar etch. By tuning the deposition conditions or incorporating some defects, it is possible to increase the thickness of the β-W [31][32][33] . In our samples the β-W is limited to 5 nm and we decided to compromise the spin hall angle efficiency in order to have a measurable device. The nanofabrication process is the same described by Tarequzzaman et al. 26 . The electron beam lithography (EBL) was used to pattern 200 nm diameter nanopillars and an ion beam milling system was used for etching. Through the secondary ion mass spectrometry incorporated into the etching system it was able to control the etch and stop within the 15 nm W layer. In order to ensure electrical isolation and physical stability, the nanopillars were buried into 800 nm SiO2 and planarized by ion beam milling with grazing incidence to expose the top of the pillar. The EBL was also used to define the HM line bottom electrode with a 6 µm length and width varying from 0.6 µm to 4.2 µm. Direct laser writing was used in the others lithographies in order to establish electrical contact with top and bottom electrodes.
After the nanofabrication, the devices were annealed at 300 ºC for 2 h, with an applied magnetic field of 1T along the same axis direction of the field used during the deposition in order to pin the synthetic antiferromagnetic layers. After the annealing the free layer of 1.4 nm CoFe40B20 exhibits in plane magnetic anisotropy 26 .

Data availability
The data that support the findings of this study are available from the corresponding author upon reasonable request.