Encoding integers and rationals on neuromorphic computers using virtual neuron

Neuromorphic computers emulate the human brain while being extremely power efficient for computing tasks. In fact, they are poised to be critical for energy-efficient computing in the future. Neuromorphic computers are primarily used in spiking neural network–based machine learning applications. However, they are known to be Turing-complete, and in theory can perform all general-purpose computation. One of the biggest bottlenecks in realizing general-purpose computations on neuromorphic computers today is the inability to efficiently encode data on the neuromorphic computers. To fully realize the potential of neuromorphic computers for energy-efficient general-purpose computing, efficient mechanisms must be devised for encoding numbers. Current encoding mechanisms (e.g., binning, rate-based encoding, and time-based encoding) have limited applicability and are not suited for general-purpose computation. In this paper, we present the virtual neuron abstraction as a mechanism for encoding and adding integers and rational numbers by using spiking neural network primitives. We evaluate the performance of the virtual neuron on physical and simulated neuromorphic hardware. We estimate that the virtual neuron could perform an addition operation using just 23 nJ of energy on average with a mixed-signal, memristor-based neuromorphic processor. We also demonstrate the utility of the virtual neuron by using it in some of the μ-recursive functions, which are the building blocks of general-purpose computation.


I. INTRODUCTION
Neuromorphic computers perform computations by emulating the human brain [1].Akin to the human brain, they are extremely energy efficient in performing computations [2].For instance, while CPUs and GPUs consume around 70 W and 250 W of power, a neuromorphic computer consumes around 65 mW of power, i.e. 4-5 orders of magnitude less power than CPUs and GPUs [3].The structural and functional units of neuromorphic computation are neurons and synapses, which can be implemented on digital or analog hardware [4].They impart critical characteristics to neuromorphic computing such as co-located processing and memory, eventdriven computation, massively parallel operation and inherent scalability [5].These characteristics are crucial for the energy efficiency of neuromorphic computers.For the purposes of this paper, we define neuromorphic computing as any computing paradigm (theoretical, simulated, or hardware) that performs computations by emulating the human brain, i.e., by using neurons and synapses, that communicate with binary-valued signals (also known as spikes).
Neuromorphic computing is primarily used in machine learning applications, almost exclusively leveraging spiking neural networks (SNN) [6].In the recent years however, it has also been used in non-machine learning applications such as graph algorithms, boolean linear algebra and neuromorphic simulations [7]- [9].Researchers have also shown that neuromorphic computing is Turing-complete, i.e. capable of generalpurpose computation [10].This ability to perform generalpurpose computations and potentially use orders of magnitude less energy in doing so is why neuromorphic computing is poised to be an indispensable part of the energy-efficient computing landscape in the future.However, in order to realize a fully operational, general-purpose neuromorphic computer, we must address several limitations of today's neuromorphic computing at the hardware and software level.
One of the biggest limitations of neuromorphic computing today is the inability to encode numbers efficiently [11].While there are several studies on the performance of neural network models with low precision representation of parameters such as weights [12], these approximate representations are not suitable for general purpose computing.There exist several methods to encode numbers on neuromorphic computers [13].However, their scope is restricted to the specific application for which they were designed and is not suitable for generalpurpose computation.Furthermore, no good mechanism exists for encoding negative integers and positive and negative rational numbers exactly on neuromorphic computers.The ability to encode basic data types such as numbers, letters and symbols is vital for any computing platform.Efficient mechanisms for encoding rational numbers would significantly expand the scope of neuromorphic computing to new application areas such as non-SNN-based machine learning (regression, support vector machines etc.), wide range of graph and network problems, general-purpose computing applications, linear and non-linear optimization, simulation of physical systems and perhaps even finding good solutions to NP-complete problems.Working with rational numbers is II.RELATED WORK Neuromorphic computing was introduced by Carver Mead in the 1980s [15].Since then, it is primarily used for SNNbased machine learning applications, including computer vision [16], natural language [17] and speech recognition [18].These applications are mainly found in embedded systems, edge computing and Internet of Things (IoT) settings as they have strict requirements for small size, weight and power [19]- [21].Several on-chip as well as off-chip learning algorithms that leverage gradient-based as well as local learning rules have been suggested for training SNNs in neuromorphic applications [22]- [25].Neuromorphic computing has also been used in neuroscience simulations [26].These simulations span a wide range of neuron and synapse models, the most popular of which is the leaky-integrate-and-fire (LIF) neuron model [27].Our virtual neuron will use spiking neurons that are of the LIF type as well.The latest additions to the arsenal of neuromorphic computing applications include graph algorithms [7], [28], [29], autonomous racing [30], epidemiological simulations [9], classifying supercomputer failures [31], µrecursive functions [10], and boolean matrix-vector multiplication [8].With regards to designing neuromorphic algorithms, a theoretical framework for determining the computational complexity has also been proposed [32].
Most of the above applications are based on binary numbers and Boolean arithmetic.This is largely due to the spiking behavior of the neuron-the spikes can be interpreted as a 1, whereas lack of spike can be interpreted as a 0. This spiking behavior naturally lends itself to binary or Boolean operations.Leveraging this behavior, several mechanisms for encoding numbers (mainly positive integers) have been proposed in the literature.Choi et al. propose a neuromorphic implementation of hypercolumns, including mechanisms for encoding images [33].Cohen et al. use neuromorphic methods to classify images that have been encoded as spikes [34].Hejda et al. present a mechanism for encoding image pixels as rate-coded optical spike trains [35].Sengupta and Roy encode neural and synaptic functionalities in electron spin as an efficient way to perform neuromorphic computation [36].Yi et al. propose a field programmable gate array (FPGA) platform to be used as a spike time dependent encoder and dynamic reservoir in neuromorphic computers [37].
Iaroshenko and Sornborger propose neuromorphic mechanisms for encoding binary numbers, and use it for binary two's complement operations and binary matrix multiplication [38].However, their approach uses numbers of neurons and synapses that are of the quadratic and cubic order respectively.Lawrence et al. perform neuromorphic matrix multiplication by using an intermediate transformation matrix for encoding that is flattened into a neural node [39].Schuman et al. propose three ways of encoding positive integers on neuromorphic computers, which are in turn used in many different applications [13].Zhao et al. develop a compact, low power, and robust spiking-time-dependent encoder, designed with a LIF neuron cluster and a chaotic circuit with ring oscillators [40].Zhao et al. develop a method for representing data using spike time dependent encoding that efficiently maps a signal's amplitude to a spike time sequence representing the input data [41].Zhao et al. propose an analog temporal encoder for making neuromorphic computing robust and energy efficient [42].Wang et al., made use of radix encoding of spike to realize SNNs more efficiently and improve the speedup by reducing the overall latency for machine learning applications [43].Other efforts to realize basic computations on neuromorphic platforms leveraging the inherent structure and parameters of SNNs for logic operations such as AND, OR and XOR have been demonstrated in [44].George et al., performed IEEE 754 compliant addition using SNNs by designing a system based on the Neural Engineering Framework (NEF) and implemented, simulated, and tested the design using Nengo [45].This approach uses an ensemble of 300 neurons to represent each bit and the function of each component in the adder is approximated using NEF to determine the appropriate synapse weights.Dubey et al., extend this work to perform IEEE 754 compliant multiplication using the same encoding method and similar methodology of using NEF to approximate the functions of the multiplier sub-components [46].
Most of these encoding mechanisms have the ability to encode binary or Boolean numbers, with some being able to encode positive integers as well.These methods are designed with specific applications in mind such as image applications, and it is not clear if they can be used for general-purpose neuromorphic computation, where arithmetic operations need to be performed on positive and negative integers/rationals.Moreover, some of the encoding mechanisms such as binning tend to lose information by virtue of discretization.To the best of our knowledge, an efficient mechanism for encoding positive and negative rational numbers does not exist in the neuromorphic literature yet.We address this gap by proposing the virtual neuron.In our quest for general-purpose, energyefficient neuromorphic computing, being able to encode rational numbers is a critical milestone.

III. NEUROMORPHIC COMPUTING MODEL
Neuromorphic computing systems implement vastly different neuron and synapse models, and the precise model details depend on the specific hardware implementation.We leverage the neuromorphic computing model described in [10] and [32], which is based on the LIF neuron with two parameters (threshold, ν and leak λ), and two synapse parameters (weight, ω and delay, δ).

IV. THE VIRTUAL NEURON
Structurally, the virtual neuron is composed of a group of LIF neurons and synapses that are connected in a particular way.Functionally, the virtual neuron mimics the behavior of an artificial neuron with identity activation.The virtual neuron is an encoding mechanism as well as an adder.It performs the addition operation similar to a ripple carry adder.The rationale behind the encoding mechanism of the virtual neuron is rooted in the binary encoding of numbers.Figure 1 shows three ways of encoding four bit numbers on a neuromorphic computer.Notice that each neuron in the figure represents a bit.The synapse coming out of the neuron assigns a value to the binary spike of the neuron by multiplying it with its synaptic weight.By having powers of two as the synaptic weights, we can encode rational numbers using a group of neurons.For instance, the synapses coming out of the four neurons in Figure 1a have weights 2 0 , 2 1 , 2 2 and 2 3 .When the second and fourth neurons (from the bottom) spike, the result gets multiplied by 2 and 8 in the outgoing synapses respectively.This is interpreted as the number 10 under this encoding mechanism.Similarly, we can set the synaptic weights to be negative powers of two as shown in Figure 1b.This enables us to encode positive fractions as well.When the first and third neurons (from the bottom) spike as shown in the figure, the result is interpreted as a 0.625.Lastly, if the synaptic weights are set to negatives of positive and negative powers of two as shown in Figure 1c, we can encode negative rational numbers.When the three neurons spike in the figure, the output is interpreted as −3.5.
We now show how the virtual neuron can integrate the incoming signals and generate a rational number as output.For ease of explanation, we stick to the two-bit virtual neuron as shown in Figure 2. The two-bit virtual neuron takes as input two 2-bit numbers X and Y , shown in the figure as [x 1 , x 0 ] (blue neurons) and [y 1 , y 0 ] (yellow neurons) respectively.It then adds X and Y in the three groups of bit neurons, which are shown in red.We call them bit neurons because they are responsible for the bit-level operations in the circuit such as bitwise addition, propagating the carry bit etc.Finally, it produces a 3-bit number Z as output, shown in the figure as [z 2 , z 1 , z 0 ] (green neurons).
The default internal states of all neurons are set to −1.Furthermore, all neurons have a leak of 0, which means they reset to their default internal state instantaneously if they do not spike.The reset state (or reset voltage) of all neurons is set to −1, so that the internal state of all neurons will be reset to −1 after they spike.The numbers on the neurons indicate their thresholds, for e.g., the top set of bit neurons (red neurons) have thresholds 0, 1 and 2 respectively.The synapse parameters are indicated in angular brackets on top or bottom of the synapses.The first parameter is the synaptic weight and the second parameter is the synaptic delay.If a group of synapses has the same parameters, it is indicated using a dotted arc.The synaptic delays are adjusted such that the bit operations of red neurons are synchronized and the output Z is produced at the same time.
We now go over the inner workings of the virtual neuron shown in Figure 2 by taking the example: We start our analysis when the inputs X and Y have been received in the blue and yellow neurons-let us call this the zeroth time step.In the first time step, the bottom set of bit neurons in red receive an input of 1 along each of their incoming synapses.Thus, the total incoming signal at both these neurons is 2, which changes their internal state from −1 to 1.As a result, both the bottom red neurons spike.Their spikes are sent along their outgoing synapses, which delay the signal for 3 time steps.
In the second time step, the middle group of bit neurons receive all of their inputs: 1 from the blue incoming neuron representing x 1 , 0 from the yellow neuron representing y 1 and 1 from the bit neuron with a threshold of 1 in the bottom group.Thus, sum of their incoming signals is 2 and their internal states reach a value of 1.As a result, neurons with thresholds 0 Fig. 2. Two-bit virtual neuron.Takes two 2-bit numbers as input on the left: X and Y , represented as x 1 , x 0 and y 1 , y 0 respectively.Adds the two numbers and generates their sum on the right.The sum of two 2-bit numbers can at most be a 3-bit number.and 1 in the middle group of bit neurons spike, whereas the one with threshold 2 does not spike.The spikes from the middle red neurons with thresholds 0 and 1 are sent to the green output neuron representing z 1 along their outgoing synapses, which stall for 2 time steps.
In the third time step, the three bit neurons in the top group of red neurons receive an input of 1 along each of their incoming synapses.As a result, their internal states are incremented by 1 to the value of 0. The neuron with 0 threshold spikes as a result and sends its spike along its outgoing synapse to the green neuron representing z 2 .
In the fourth time step, the green neurons representing z 0 , z 1 and z 2 receive their inputs.z 0 receives a 1 and −1 from the bit neurons with the thresholds 0 and 1 respectively in the bottom group of red neurons.Its total input is thus 1 − 1 = 0, which keeps its internal state at −1, and it does not spike.Similar operations happen at the green neuron representing z 1 .It too does not spike.The green neuron representing z 2 receives a signal of 1 from the bit neuron with the threshold of 0 in the top red set.As a result, its internal state is incremented by 1 to the value of 0, and it spikes.
The net output [z 2 , z 1 , z 0 ] from the circuit is [1, 0, 0], which can be interpreted as a 4 in binary.Given that our inputs were [x 1 , x 0 ] = [1,1], and [y 1 , y 0 ] = [0, 1], i.e., X = 3, and Y = 1, we have received the correct output of 4 from the virtual neuron circuit.While we restricted ourselves to 2-bit positive integers in this example, we show in the subsequent subsections that similar circuits can be used to encode and add two rational numbers in the virtual neuron and generate a rational number as output.Finally, note that we did not use powers of two in the synapses inside of the virtual neuron.Depending on the application, powers of two as synaptic weights may be used on the incoming or outgoing synapses for a given virtual neuron.
We now describe the connections for a virtual neuron with arbitrary precision.Each input neuron has both threshold and leak as zero.Each input x i and y i is connected to the set of bit neurons corresponding to bit i.In the case of bit 0 there are two such bit neurons, while for every other bit, there are three neurons per bit shown in red.The synaptic weights of all these connections are unity and their delays are i + 1.Each set of bit neurons has neurons with thresholds of zero and one.All bit neurons except the zero bit have a neuron with Fig. 3. P + bit virtual neuron for encoding positive integers.Synapse parameters are omitted for brevity.Actual synapse parameters are assumed to be similar to the circuit shown in Figure 2. a threshold of two as well.The neuron with a threshold of one in the set of neurons representing bit i is connected to all neurons in the (i + 1)-th set.This neuron is responsible for the propagating the carry bit to the next set of bit neurons.It spikes only when there is a carry operation to be performed at the i-th bit.The carry synapses have both weights and delays as unity.The bit neurons of the i-th bit are connected to the i-th output neuron.The synaptic weights for the bit neurons having thresholds of zero and two are 1, while those for the bit neurons having threshold of one are −1.The −1 weight is seen as an inhibitory connection that cancels the signal coming from the neuron with threshold zero in the same bit set.The delays on the synapses going from i-th bit set to the i-th output neuron are set to max{P + , P − } − i + 1.This delay ensures that all output neurons spike at the same time.

A. Positive Integers
Figure 3 shows the virtual neuron circuit that takes two P + bit numbers X and Y as inputs, shown as blue and yellow neurons respectively.The bit-level addition and carry operations are performed by the bit neurons shown in red.There are P + + 1 groups of these bit neurons.Finally, the output of the virtual neuron Z has P + + 1 bit precision, and is shown by the green output neurons.In the figure, we omit synapse parameters for brevity.Notice that the synaptic weights on the outgoing synapses are positive powers of 2.

B. Positive Fractionals
Figure 4 shows the P + bit virtual neuron for encoding positive fractionals.The circuit is almost identical to Figure 3.The only difference is in the synaptic weights of the outgoing synapses.In this case, these synapses have negative powers of two, i.e., 2 0 , 2 −1 , 2 −2 , 2 −3 , . . .as their weights.
Fig. 4. P + bit virtual neuron for encoding positive fractionals.Synapse parameters are omitted for brevity.Actual synapse parameters are assumed to be similar to the circuit shown in Figure 2.

C. Negative Integers
Figure 5 shows the virtual neuron circuit for encoding negative integers.It takes two P − bit numbers X and Y as inputs.After standard virtual neuron operations, a P − + 1 bit number Z is produced as the output.In this case, these weights are negatives of positive powers of two, i.e., −2 0 , −2 1 , −2 2 , . ...

D. Negative Fractionals
Figure 6 shows the P − bit virtual neuron circuit for encoding negative fractionals.This circuit is identical to Figure 5, Fig. 6.P − bit virtual neuron for encoding negative fractionals.Synapse parameters are omitted for brevity.Actual synapse parameters are assumed to be similar to the circuit shown in Figure 2. except the outgoing synapses have weights that are negatives of negative powers of two, i.e. −2 0 , −2 −1 , −2 −2 , . ...

E. Positive and Negative Rational Numbers
In this case, the virtual neuron operates on two P + + P − bit rational numbers X and Y as inputs.These are shown in blue and yellow rectangles, which denote aggregation of respective neurons.The positive precision P + is split between the positive integers and positive fractionals.Similarly, negative precision is split between the negative integers and negative fractionals.Notice that the positive part of the circuit (upper half) is completely independent from the negative part of the circuit (lower half).

F. Computational Complexity
For P + bit positive operations, we use O(P + ) neurons and synapses, and perform the virtual neuron operations in O(P + ) time steps.Similarly, for P − bit negative operations, we use O(P − ) neurons and synapses, and perform the virtual neuron operations in O(P − ) time steps.All in all, we use O(P + +P − ) neurons and synapses, and consume O(max{P + , P − }) time steps for the virtual neuron operations.
We validate these space and time complexities empirically for positive operations by increasing P + .The results of this analysis apply to negative operations as well.We increase the positive precision from 1, 2, 4, . . ., 128 and count the number of neurons, synapses and time steps in each case.The We can extend these time complexities to negative operations to conclude that they would require 6P − + 3 neurons, 12P − synapses and P − +2 time steps.This validates the space complexity as needing O(P + + P − ) neurons and synapses.Since the positive and negative operations happen parallely, the overall time complexity of the circuit would stem from the larger of P + and P − .So, the overall time complexity is validated as O(max{P + , P − }).
Lastly, in computing the above space and time complexities, our inherent assumption is that the positive and negative precisions are variable.However, we envision using the virtual neuron in settings where a neuromorphic computer has a fixed predetermined positive and negative precision.This is similar to how the precision on our laptops and desktops is fixed to 32, 64 or 128 bits.In such a scenario, P + and P − can be treated as constants.Thus, the resulting space and time complexities for virtual neuron would all be O(1).
Table II presents a comparison of different neuromorphic encoding approaches in the literature with our approach using the virtual neuron.Since a neuromorphic computer consumes energy that is proportional to the number of spikes, we use the number of spikes in the worst and average case as an estimate for the energy usage of different neuromorphic approaches.It can be seen that across different comparison metrics such as network size, or number of spikes, the virtual neuron scales linearly with the bit-precision N , while giving the exact representation of the input number.Other approaches take either exponential space (Binning), or exponential time (Rate Encoding), or are unable to represent rational numbers exactly (IEEE 754).Table III presents the comparison of computational complexity for performing addition with two Nbit numbers under different neuromorphic encoding schemes.Here we do not include temporal encoding scheme because under such a simple approach, binary spikes occurring at different time instances cannot be added in an exact manner by spiking neurons.While the virtual neuron can perform the addition operation in linear time steps and using linear number of neurons, synapses and energy (as estimated by the spiking efficiency), other approaches use either exponential time or exponential space or consume exponential amount of energy for their operations.

V. IMPLEMENTATION DETAILS
We implemented the virtual neuron in Python using the NEST simulator.The hardware on which the simulations were run was a MacBook Pro having a 2.3 GHz Quad-Core Intel Core i7 processor and 32 GB 3733 MHz LPDDR4X memory.We wrote a VirtualNeuron class, whose constructor took a list-like object of length 4 as the precision vector.The elements of this vector corresponded to number of bits for positive integers, positive fractionals, negative integers and negative fractionals.We then computed the positive precision as the sum of the first two elements of the precision vector, and the negative precision as the sum of the third and fourth elements of the precision vector.
We then created all the neurons and set their parameters correctly.We used the iaf_psc_delta neuron model.All neurons had an internal state of −1.0.In NEST, the internal state corresponds to the voltage of the membrane potential (V_m) parameter.All neurons had a leak of 10 −6 , which is a good approximation to 0 leak that we require in our circuits.In NEST, the leak corresponds to the tau_m neuron parameter.All neurons except the bit neurons (red neurons) had a neuron threshold of 0. The group of bit neurons corresponding to the least significant bit in both the positive and negative parts of the circuit had only two neurons with thresholds 0 and 1.All other groups of bit neurons had three neurons with thresholds 0, 1 and 2 respectively.There were P + (P − ) such groups in the positive (negative) part of the circuit, making a total of P + + 1 (P − + 1) groups of bit neurons, corresponding to the P + + 1 (P − + 1) output bits in the positive (negative) parts of the circuit.
After the neurons were created, we setup the synapses.Firstly, synapses between the positive (negative) incoming neurons and positive (negative) bit neurons were created.These synapses had synaptic weights as 1.0 and synaptic delays as i+1, where i ranges from 0 to P + (P − ).Secondly, we setup the carry synapses between the consecutive groups of positive (negative) bit neuron groups.The carry synapses go from the bit neuron having a threshold of 1 in the i th group to all neurons in the (i + 1) th group, where i goes from 0 to P + (P − ).The carry synapses had both weights and delays as 1.0.Finally, we setup synapses from groups of positive (negative) bit neurons to their corresponding outgoing neurons.The synapses coming from bit neurons with thresholds 0 and 2 had weights 1.0, whereas those coming from bit neurons with thresholds 1 had weights of −1.0.Furthermore, these syapses in the positive (negative) part of the circuit had delays given by max{P + , P − } − i + 1 for i ranging from 0 to P + (P − ).We also wrote a function connect_virtual_neurons(A, B, C), that connects three virtual neurons A, B and C such that A and B serve as inputs to C. The weights and delays on these synapses were all 1.0.

VI. TESTING RESULTS
We tested our implementation of the virtual neuron on 8, 16 and 32 bit rational numbers.The precision vectors fed to the class constructors in each of these cases were [2, 2, 2, 2], [4,4,4,4], and [8,8,8,8] respectively.We connected three virtual neurons using the connect_virtual_neurons function described above.Next, we generated two numbers within the appropriate precision by generating spikes through the spike_generator in NEST, and then sent these spikes to the input virtual neurons A and B. We let the simulation run for a time long enough so that we receive an output from virtual neuron C. Lastly, we checked if output received from C was indeed the sum of numbers sent to A and B.

A. 8 Bit Virtual Neuron
For the 8 bit case, we tested all permutations of the input numbers-a total of 65, 536 cases.A randomly selected sample of results are shown in Table IV.It can be seen clearly that X + + Y + = Z + , and X − + Y − = Z − for all rows.The binary representations of X and Y were fed to the input neurons and the binary representation of Z was received as the output of the circuit.

B. 16 Bit Virtual Neuron
The results from the 16 bit testing are shown in Table V.In this case, we tested 100, 000 permutations of inputs, generated uniformly at random.A snippet of the results are shown in Table V.One can infer that the virtual neuron is mimicking an artificial neuron having an identity activation function, and that we are able to encode positive and negative rational numbers on a neuromorphic computer using this approach.

C. 32 Bit Virtual Neuron
For the 32 bit case, we generated 100, 000 permutations of inputs uniformly at random.Five randomly selected permutations are presented in Table VI.Once again, it can be concluded that the virtual neuron is successfully able to encode and add rational numbers on neuromorphic computers and scales linearly with the positive and negative precisions.

D. Caspian and Hardware Testing
We also implemented and tested the 16-bit virtual neuron using the Caspian simulator and µCaspian digital FPGA hardware [47].Since µCaspian does not implement synaptic delay, but instead implements axonal delay, the virtual neuron implementation was adjusted to use axonal delay instead of synaptic delay.The rest of the structure is the same as the NEST virtual neuron implementation, this means that the neuron and synapse counts and network time steps to solution are the same as in the NEST implementation.
µCaspian is a digital neuromorphic processor implementation using an FPGA, the processor is event-based and processes all the spikes that occur at one time step before moving to the next time step.Time multiplexing of neurons is used to reduce the size of the design.µCaspian is intentionally designed targeting the small and low-power iCE40 UP5k FPGA.Because of this, µCaspian only supports up to 256 neurons and 4096 synapses.This is enough to support up to a 32-bit virtual neuron adder; however, to include room for the input and output neurons, we tested with the 16-bit virtual neuron.Since µCaspian run time depends on activity, we ran 1,000 permutations of inputs selected uniformly at random on the µCaspian simulator and hardware, and monitored the total number of spikes and the number of cycles used by the processor.µCaspian has a behaviourally accurate software simulator and the hardware design can be emulated in Verilator or run on the FPGA.In this case we used the UPdruino V3 as the FPGA board.
Over the 1,000 runs, the simulator reported 73,159 total spikes for an average of 73 spikes per test case.Using Verilator, the 1,000 test cases finished in ∼ 5,000,000 clock cycles.Where ∼ 7,000 cycles where used to load the virtual neuron network and ∼ 5,000 cycles are used per test case.Since the processor runs at 25 MHz, the total runtime without the overheads from communication with the host computer is ∼ 0.21s for all the test cases.When we ran the test using the UPduino FPGA, the total time was ∼ 400s.One main culprit for this slowdown is the 3 MBaud UART connection between the host and the FPGA.While running on hardware, over 99.9% of the execution time was spent in overhead and communication.This result highlights the great benefit of using the virtual neuron to perform addition on the SNN system instead of moving the data to a separate processor to perform the addition.The results from the hardware evaluation are tabulated in Table VII and a summary of the µCaspian processor cycles from the experiment are in Table VIII.

E. mrDANNA Power Estimate
With neuromorphic application-specific integrated circuits, the power required for a particular network execution can be estimated based on the energy required for active and idle neurons and synapses for the duration of the execution.To estimate the power of the virtual neuron design, we used the same method and energy-per-spike values as reported in [48] for the mrDANNA mixed-signal memristor-based neuromorphic processor.Using the same number of spikes, neurons, and synapses as reported in the µCaspian simulation, we estimate that a mrDANNA hardware implementation would use ∼ 23 nJ for the average test case run and around ∼ 23 mW for continuous operation.

VII. APPLICATIONS
In this section, we look at five functions where virtual neuron is used: constant function, successor function, predecessor function, multiply by −1 function, and N -neuron addition.

A. Constant Function
For a natural number x, the constant function returns a constant natural number k.It is defined as:  Figure 8 shows the neuromorphic circuit that computes the constant function.It has been adapted from [10] to work with the virtual neuron.Each neuron in this circuit is a virtual neuron.Inputs k and x are fed to the input neurons 0 and 1, and the output is produced at neuron 2. Synapses going from neuron 0 to neuron 2 have weights of 1, while those going from neuron 1 to neuron 2 have weights of 0. The constant function is one of the µ-recursive functions.µrecursion is a model of computation that is equivalent to the Turing machine.In order to prove that a computing platform is Turing-complete, it suffices to prove that it can execute all the µ-recursive functions.In that light, being able to implement the constant function is a step towards empirically showing that neuromorphic computing is Turing-complete.We implemented the constant function circuit in NEST and tested it with 16 bit natural numbers.We were able to accurately execute the constant function using virtual neurons.

B. Successor Function
For a natural number x, the successor function returns x+1.The successor of 0 is defined as 1.The successor function is defined as: Figure 9 shows the successor function.It too has been adapted from [10] and is another µ-recursive function.It is similar to the constant function with a couple of differences.Neuron 0 is fed an input of 1 and synapse (1,2) has a weight of 1.We implemented the successor function using three virtual neurons and tested it on 16-bit numbers.Our implementation was able to execute the successor function successfully.

C. Predecessor Function
For a natural number x, the predecessor function returns x − 1.The predecessor function is defined as: Figure 10 shows the predecessor function.It is similar to the successor function with just one change.We feed an input of −1 to neuron 0 as opposed to 1.We implemented the predecessor function using three virtual neurons and tested it on 16 bit numbers.We were able to execute the predecessor function successfully using three virtual neurons in NEST.

D. Multiply by -1
For a rational number x this function returns −x. Figure 11 shows the multiply by −1 function.It takes a rational number encoded in virtual neuron X.In the figure, we use X + to denote the positive part of X and X − to denote negative parts of X.In this function, we assume that the number of positive and negative precision bits are equal.Under this assumption, we simply swap the positive and negative parts of X to return a number Z encoded as a virtual neuron.Since Z + equals X − and Z − equals X + , this function returns the negative of a number fed as the input.We implemented this function on 16 bit numbers and found that our virtual neuron-based implementation was able to execute the function successfully.

E. N-Neuron Addition
The last application of virtual neuron that we want to highlight is the N -neuron addition.The figure for this application is shown in Figure 12, where we would like to add N virtual neurons given as inputs.The addition is performed by successfully connecting pairs of input virtual neurons to a layer of virtual neurons, which in turn serve as inputs to the next layer.This method uses O(N ) virtual neurons and synapses and runs in O(log N ) time steps.We implemented the N -neuron addition circuit in NEST and tested it on 16 bit numbers.This implementation was successfully able to add N virtual neurons in O(log N ) time.

VIII. DISCUSSION
In this paper, we proposed the virtual neuron as a mechanism for encoding as well as adding positive and negative rational numbers.Our work is a stepping stone towards a broader class of neuromorphic computing algorithms, that would enable us to perform general-purpose computations on neuromorphic computers.In this paper, we also measured the time, space, and energy required for virtual neuron operations and showed that it takes around 23 mW of power.In addition to a low operational power, there will be great savings in performing the operation withing the spiking array, without the need to spend energy sending the data to an external processor to perform the operation.Although it is out of the scope of this paper, the virtual neuron is a vital component to enabling composing of sub-networks to scale-up neuromorphic algorithms, and it is also a vital component to support within network encoding and decoding capabilities.We would like to address these areas as part of our future work.
The virtual neuron can be viewed as a tool that enables bitlevel precision as well as variable precision on neuromorphic computers.We also expect the virtual neuron to be used in neuromorphic compilers that can compile high-level neuromorphic algorithms down to neurons and synapses, which can be deployed onto neuromorhpic hardware directly.Another potential use case of the virtual neuron is to encode and perform operations on extremely large numbers (containing thousands of bits), as required in many cryptography applications.The virtual neuron would enable us to perform these large number operations in an energy efficient manner on neuromorphic computers.In an edge computing scenario, current neuromorphic computers allow us to perform machine learning tasks using spiking neural networks in an energyefficient manner.However, if an application requires performing general-purpose operations on data (for instance, pre-or post-processing of data using arithmetic, logical and relational operations), we resort to conventional computers (CPUs and GPUs), which incurs significant communication cost.With approaches such as virtual neuron that serve as the building blocks of general-purpose computing on neuromorphic computers, we could potentially perform all these operations on the neuromorphic computer itself without having to communicate to the CPU/GPU and bypassing the need to transfer data back and forth from the CPU/GPU.
It is worth noting that the ultimate goal of a neuromorphic computer is not to perform these sorts of operations.However, many applications for which a neuromorphic system might be used (for classification, anomaly detection, control, etc.) may require these sorts of calculations as a pre-or post-processing step for the neuromorphic system.For a continually operating neuromorphic system, for example in a control application, these sorts of calculations may be required between neuromorphic calculations.If these computations can take place on the neuromorphic computer, then it will alleviate communication costs and data movement to and from the neuromorphic system.As such, even if the computations described above are not as efficient as those on a traditional processor, it is likely that the data movement costs to and from the traditional processor will overwhelm the energy efficiency benefits gained from moving the computation back to a traditional processor.
Just like with IEEE standard data types, real numbers such as √ 2, π and e cannot be directly encoded without infinite bits of precision.Therefore the bits of precision used in the virtual neuron encoding can be chosen based on the accuracy of the approximation of the real number required.Lastly, the applications demonstrated in Section VII might seem simple, but they are critical building blocks for any general-purpose computations that can be performed on a neuromorphic computer.Complex general-purpose compute tasks can be broken down into the simplest of operations defined by these functions.We would like to reiterate that the goal of this paper was to present the idea of the virtual neuron and demonstrate its performance on physical and simulated neuromorphic hardware.The demonstration on the applications mentioned in Section VII is to give the reader an idea of how the virtual neuron can be used.

IX. CONCLUSION
Neuromorphic computing is an extremely promising paradigm for energy efficient computing in the future.It holds tremendous promise to drastically reduce the carbon footprint of computing.While traditional applications of neuromorphic computing primarily relied on SNN-based machine learning, more recent applications in graph algorithms, autonomous racing and linear algebra show that neuromorphic computing might be capable of much more than just SNNs.Neuromorphic computing has shown to be Turing-complete, and thus, capable of all general-purpose computation.A key step to realize the full potential of general-purpose neuromorphic computing is to devise effective mechanisms of encoding numbers.The current mechanisms for encoding numbers on neuromorphic computers are limited to Boolean numbers or natural numbers.But even these mechanisms are limited to the specific applications for which they were developed, and are not suitable for general-purpose computation.Moreover, some of these methods result in loss of data due to excessive discretization and/or do not preserve addition.
In this work, we presented the virtual neuron as a mechanism for encoding positive and negative integer and rational numbers.We implemented the virtual neuron in the NEST simulator and tested it on 8, 16 and 32 bit rational numbers.We theoretically compared the computational complexity of the virtual neuron to other neuromorphic encoding mechanisms.Next, we tested the virtual neuron on neuromorphic hardware and presented its time, space and power metrics.
Lastly, we demonstrated the usability of the virtual neuron by using it in five applications, that would be crucial for general-purpose neuromorphic computing.We were able to show that the virtual neuron is an efficient mechanism for encoding rational numbers.Furthermore, we also showed that the virtual neuron can mimic the artificial neuron with an identity activation function.In our future work, we would like to explore general-purpose neuromorphic algorithms and applications using virtual neurons.

Fig. 1 .
Fig. 1.Encoding mechanism of the virtual neuron.Numbers can be encoded by selecting appropriate synaptic weights.Here, we use four neurons to encode: (1a) positive integers; (1b) positive rationals; and, (1c) negative rationals.The four spiking neurons can encode four bits of information.

Fig. 5 .
Fig.5.P − bit virtual neuron for encoding negative integers.Synapse parameters are omitted for brevity.Actual synapse parameters are assumed to be similar to the circuit shown in Figure2.

TABLE I NEURONS
, SYNAPSES AND TIME TAKEN WITH INCREASING PRECISION.
1Dimension refers to the number of values represented by the ensemble.(Forascalar quantity this is 1).Radius defines the range of values that can be represented by the ensemble.For the cited work dimension is 1 and radius is set to 2.2Authors only looked at IEEE floating point, so how the representation scales with numerical precision is unclear.

TABLE III COMPARING
VIRTUAL NEURON TO OTHER NEUROMORPHIC ENCODING MECHANISMS FOR ADDING TWO N-BIT NUMBERS.Accuracy is bound by the synapse weight and accumulation accuracy.numerical results are presented in Table I.From the table, we can conclude that we use 6P + + 3 neurons, 12P + synapses and P + + 2 time steps for virtual neuron operations.

TABLE IV TESTING
VIRTUAL NEURON ON 8-BIT RATIONAL NUMBERS.PRECISION IS [2, 2, 2, 2] FOR POSITIVE INTEGER, POSITIVE FRACTION, NEGATIVE INTEGER AND NEGATIVE FRACTION RESPECTIVELY.

TABLE VI TESTING
VIRTUAL NEURON ON 32-BIT RATIONAL NUMBERS.PRECISION IS [8, 8, 8, 8] FOR POSITIVE INTEGER, POSITIVE FRACTION, NEGATIVE INTEGER AND NEGATIVE FRACTION RESPECTIVELY.