Ternary logic decoder using independently controlled double-gate Si-NW MOSFETs

A ternary logic decoder (TLD) is demonstrated with independently controlled double-gate (ICDG) silicon-nanowire (Si-NW) MOSFETs to confirm a feasibility of mixed radix system (MRS). The TLD is essential component for realization of the MRS. The ICDG Si-NW MOSFET resolves the limitations of the conventional multi-threshold voltage (multi-Vth) schemes required for the TLD. The ICDG Si-NW MOSFETs were fabricated and characterized. Afterwards, their electrical characteristics were modeled and fitted semi-empirically with the aid of SILVACO ATLAS TCAD simulator. The circuit performance and power consumption of the TLD were analyzed using ATLAS mixed-mode TCAD simulations. The TLD showed a power-delay product of 35 aJ for a gate length (LG) of 500 nm and that of 0.16 aJ for LG of 14 nm. Thanks to its inherent CMOS-compatibility and scalability, the TLD based on the ICDG Si-NW MOSFETs would be a promising candidate for a MRS using ternary and binary logic.

Scalability is one of the most important concerns in complementary metal-oxide-semiconductor (CMOS) device and circuit design 1 . Over the past several decades, the metal-oxide-semiconductor field-effect transistor (MOSFET) has been continuously scaled down to achieve higher performance and higher packing density with lower cost. An undesirable consequence of this aggressive down-scaling has been the appearance of adverse short-channel effects (SCEs), as well as increasingly challenging fabrication limits. To mitigate the SCEs, and continue further down-scaling, innovative device structures such as FinFETs, gate-all-around (GAA) FETs and a nanosheet (NS) based FET, have been introduced [2][3][4][5][6] . These new device structures have been able to suppress the off-state current (I off ), which is fatal to the power consumption of a chip in the stand-by state. However, even with the above structural innovations, there are still limits that require device and process parameters to be continuously optimized.
Another approach to improving on-state current (I on ) and chip performance has focused on the use of new materials, such as strained Si/SiGe and III-V compound semiconductors [7][8][9] . Although the new materials have advantages, silicon is still the most attractive material when CMOS-compatibility with low-cost is considered 10 .
In the meanwhile, multi-valued logic (MVL) has also been considered promising architecture to overcome the MOSFET scaling limitations from a circuit point of views. The MVL system can reduce the burden of circuit complexity inherent to binary-based logic circuits, by converting a multiple-output Boolean function into a single-output multiple-valued function 11,12 . In one particular case, a ternary-based logic circuit reduced the total cost and power consumption by minimizing the number of required inputs, resulting in the simplification of metal interconnection, compared to other MVL systems 13 .
In spite of these potential advantages, the practicality of ternary logic design heavily relies on the availability of the device and circuitry, which must be compatible with present-day binary CMOS technologies 12 . Binary operation has been the mainstay of modern computing system. To take full advantage of ternary logic, a mixed radix system (MRS) using both ternary and binary logic would be more suitable, rather than exclusively using ternary logic. To implement a MRS, conversion from a ternary code to a binary code is essential and vice versa [14][15][16] . This requires a ternary logic decoder (TLD). Logic blocks such as a ternary logic multiplexer (TLM), a TLM-based half adder and comparator can be implemented based on the TLD 17 .
To realize a TLD, a logic scheme for multi-threshold voltage (multi-V th ) is necessary 18 . There have been two approaches used to implement a multi-V th scheme. One uses physical methods, by tuning the work-function of a metal gate 19 and by modulating the channel or body doping concentration by ion implantation 20 . The other utilizes electrical methods, applying back bias to a body in the MOSFET or potential redistribution in a gate electrode 21  www.nature.com/scientificreports/ engineering increases process complexity, and limits the spectrum of potential materials, which can lead to a work function variation (WFV) problem given the variability in grain size 22 . Adjustment of V th by ion implantation also involves issues with complementary dopants, accurate depth and concentration control, diffusivity, implantation-induced damages, and random dopant fluctuations. Moreover, channel doping concentration has little effect on V th control for a thin gate dielectric and a fully-depleted thin-body channel [23][24][25] .
With the electrical approach, additional static back bias in the bulk planar MOSFET increases parasitic capacitance and leakage, which can degrade device performances. In any case, fine tuning the V th is not an easy task, because V th modulated by applied static back bias does not follow a linear relationship. In addition, the static back bias can degrade I off and subthreshold swing (SS). For the gate electrode potential redistribution method, another challenging issue has been observed, an increase in static power consumption 21 .
In another approach, a previous study attempted to control V th dynamically by using the four-terminals of an independently controlled double-gate (ICDG) FinFET 26─31 . Such a novel device could mitigate the abovementioned problems by allowing multi-V th . But, there have been no reports of using ICDG devices for TLD so far. A primary goal of the present work is to demonstrate a TLD composed of ICDG silicon-nanowire (Si-NW) MOS-FETs, and to confirm the feasibility of manufacturing a MRS chip. Because of their inherent CMOS-compatibility and simplicity, the proposed TLD would be a promising option for realizing a mixed radix circuit.

Results and discussion
Supplementary Fig. S1 shows a simplified sequence of the experimental details. N-channel ICDG Si-NW MOS-FETs were fabricated, modeled, and fitted semi-empirically with the aid of SILVACO ATLAS TCAD simulator 32 . Thereafter, a P-channel ICDG Si-NW MOSFET was regenerated as a counter-part of the N-channel by simulations. Following device-level simulations, further analyses of the TLD circuit performance and power consumption were conducted using ATLAS mixed-mode TCAD simulations to predict the TLD behaviors at an elementary circuit level, as an extension. All of the abbreviations and nomenclature of variables are summarized in Supplementary Table S1.
Fabrication process of the ICDG Si-NW MOSFET is summarized in Supplementary Fig. S2. Figure 1 shows a schematic of the ICDG Si-NW MOSFET and scanning electron microscopy (SEM) and transmission electron microscopy (TEM), images of the fabricated ICDG Si-NW MOSFET. The fabricated ICDG Si-NW MOSFET was composed of two gates, a drive gate and a control gate, positioned at each sidewall of the Si-NW to control the current flowing in the Si-NW. The drive gate turns the channel on or off. The control gate modulates threshold www.nature.com/scientificreports/ voltage as a body electrode does in a conventional bulk-MOSFET. The fabricated device had a Si-NW width (W Si ) of 70 nm, a gate length (L G ) of 500 nm, a Si-NW height (H Si ) of 50 nm and a gate dielectric thickness (T ox ) of 10 nm. The dimensions of the modeled device were the same as the fabricated device. Source, body, and drain doping concentration were set to 1 × 10 20 cm -3 , 1 × 10 15 cm -3 , 1 × 10 20 cm -3 , respectively. Various models such as Schockly-Read-Hall (SRH), bandgap narrowing (BGN), Fermi-Dirac (FERMI), energy balance model (EBM), non-local band-to-band tunneling (BTBT), trap-assisted tunneling (TAT), and quantum effect (QUANTUM for electrons and P.QUANTUM for holes) were utilized for the simulations. The P-channel ICDG Si-NW MOSFET was modeled in the same manner as the N-channel device, except for the doping polarity and H Si . The dopant of the P-channel device was the opposite that of the N-channel device, and the H Si was doubled considering the difference in carrier mobility of electrons and holes.  (Fig. 2c) and V cGS = − 1.5 V (Fig. 2d) on the log-scaled y-axis and linear-scaled y-axis. They (measured and simulated) are very similar to each other. Because individual gate addressing is possible thanks to the use of two local gates, the channel potential of the Si-NW can be controlled independently 33 . One of the two gates is used to sweep the gate voltage of the drive gate while a constant voltage is applied to the other gate, which is the control gate to precisely tune the channel potential of the Si-NW. A shift in V th and its multiple values by V cGS are shown in Fig. 2e. The V th shift by V cGS has linear relationship. The results are consistent with the previously reported data [26][27][28][29][30][31] . As the |V cGS | increased, the I D -V dGS curve shifted rightward in parallel and the V th was increased. Herein, leakage current is defined as off-state current at V dGS of 0 V. The measured leakage current from the fabricated ICDG Si-NW NMOSFET was decreased from 10 pA to 300 fA as the |V cGS | was increased from 0.4 V to 1.5 V. Figure 2f shows the symmetrically overlaid I D -V dGS curves of the simulated N-channel and P-channel ICDG Si-NW MOSFET. Here, there is a wide overlapped region between the N-channel device and the P-channel device. This wide overlapped region stably creates a intermidiate output signal (output '1'), which enables the TLD. It becomes wider as the applied |V cGS | increases.
Note that there are negative ternary inverters (NTI) and positive ternary inverters (PTI) in ternary logic. Its output state becomes '0' or '2' when the input state is '1′ 18 as shown in Fig. 3b. The proposed TLD was composed of NTI, PTI, and negative ternary NOR (NTNOR) 18 . To implement the TLD, the characteristics of NTI and PTI should be confirmed.
As shown in Fig. 3a, the ternary inverter circuitry is similar to a typical binary inverter except for the use of the control gates. The complementary circuit shown in Fig. 3a can become both the NTI and the PTI by adjusting V cGN and V cGP . As shown in Fig. 3c, the voltage transfer curve (VTC) is shifted in parallel as |V cGNS | increases from 0.4 V to 2.1 V and |V cGPS | decreases from 2.0 V to 0.3 V. For the NTI, an input voltage (V in ) of 0.5 V (state '1') is transformed to a V out of 0 V (state '0') because |V th | in the P-channel device is higher than that of the N-channel device. In contrast, the V in of 0.5 V (state '1') is converted to a V out of 1 V (state '2') in the case of the PTI, due to the higher |V th | of the N-channel device. Figure 3d shows the I VDD and P VDD characteristics versus the V in . The I VDD increased and decreased exponentially as the N-channel and P-channel devices started to turn on and turn off, respectively, at a certain voltage. Peak points of the I VDD curve at a certain voltage, were shifted as the |V cGNS | and |V cGPS | changed. P VDD can be obtained by multiplying the I VDD by V DD for various V in , as shown in the 2nd y-axis in Fig. 3d. We can average P VDD for three states with a different weighting factor: w 0 for state '0' , w 1 for state '1' and w 2 for state '2' . This is represented by < P VDD > avg = (w 0 ⋅P VDD | state=0 + w 1 ⋅P VDD | state=1 + w 2 ⋅P VDD | state=2 )/(w 0 + w 1 + w 2 ). This averaged P VDD is approximated to (1/3)⋅w 1 ⋅P VDD | state=1 under the condition of w 0 = w 1 = w 2 , because the P VDD | state=2 and P VDD | state=0 are much smaller than the P VDD | state=1 . It should be noted that I VDD for state '1' is much larger than that at the state '0' and '2' . When the curve (green line) of a typical binary inverter in Fig. 3d is shifted to the NTI or the PTI, the P VDD | state=1 decreases. Accordingly, the total P VDD decreases.
A 1-to-3 TLD circuit was designed to examine the feasibility of the ICDG Si-NW MOSFET for the TLD. The TLD consisted of 10 complementary ICDG Si-NW MOSFETs. Figure 4a shows the TLD logic circuit and its VTCs for an output '0' , output '1' , and output '2' versus the V in . The NTNOR CMOS circuitry was the same as the typical binary NOR except for the use of the control gates. The device models for the NTNOR were identical to the device models described in Fig. 2. As shown in the VTC graph in Fig. 4a, the TLD stably accepts voltage near 0.5 V as an input then it produces the third output voltage (output '1'). The behaviors of the TLD were verified using the ATLAS mixed-mode TCAD simulations, as shown in Fig. 4b and c. Voltage levels of 1 V (V DD ), 0.5 V (half V DD ), and 0 V (V SS ) are equivalent to a logic value of '2' , '1' , and '0' , respectively. Figure 4d shows a diagram of the state transition with propagation delay time. Note that the transition time is related to on-current of a MOSFET. According to the result of Fig. 4d, t 2 ('1' → '0') was almost the same as t 5 ('2' → '0') because both the t 2 and t 5 depend on the on-current of an n-channel pull-down transistor (I on, '0' ). Likewise, t 3 ('1' → '2') was the same as t 6 ('0' → '2') because both the t 3 and t 6 depend on the on-current of a p-channel pull-up transistor (I on, '2' ). t 1 and t 4 are dominated by on-current (I on, '1' ) at an intermediate state. I on, '1' is defined as the drain current at V dGS = V DD /2. As shown in Fig. 2f, the I on, '1' was smaller than the I on, '0' and I on, '2' . Therefore, t 1 and t 4 were longer than the other transition times (t 2 , t 3 , t 5 , and t 6 ). Additionally, the difference between t 1 and t 4 was arisen from a slight disparity of I D between I on, '1' of a p-channel MOSFET and an n-channel MOSFET. The delay time (τ d ) is dominated by the longest transition time (t 1 ). To reduce the delay time, I on, '1' modulated by |V cGS | should be maximized as large as possible.
Based on SILVACO ATLAS TCAD simulator, the scaling analysis was implemented by reducing device dimensions (L G , W Si , H Si , and T ox ). The detailed information of those is shown in Supplementary Table S2. Figure 5 shows a quantitative analysis of gate capacitance (C gg ) and I on, '1' . Figures 5a and b show  www.nature.com/scientificreports/ www.nature.com/scientificreports/ V th -modulation according to V cG can be performed with consideration of two conflicting demands: maximization of speed and minimization of static power consumption. Increment of I on, '1' through the V cG modulation can result in boosting speed of the ternary logic decoder (TLD). But, excessive increment of I on, '1' can adversely increase the static power consumption (P) of the TLD owing to a parallel shift of V th , which provokes increment of leakage current. Thus, the optimization of V cG can be done with a well-known figure of merit, power-delay product (PDP) owing to the abovementioned trade-off relationship. The magnitude of C gg for N-channel and P-channel ICDG Si-NW MOSFETs was decreased as L G was decreased. As shown in Fig. 4c and d, as L G was decreased, C gg was continuously decreased, while I on, '1' was maintained by V th -modulation. It means that delay time (τ d ) of the TLD circuit is decreased by down-scaling. Figure 6a and b show two transient current responses for an L G of 500 nm and an L G of 14 nm, respectively at input voltage frequency (f in ) of 12.5 MHz. The f in of 12.5 MHz was used from T = 1/f in = 80 ns as shown in Fig. 4b first graph. When the input voltage signal abruptly switched from one state to another, charges were transferred from the power supply to the gate capacitors or load capacitors. And |I VDD | rapidly increased and temporarily overshot, thereafter it began to stabilize. As shown in Fig. 6b, the pulse width needed to induce the overshoot was significantly reduced by down-scaling from L G = 500 nm to L G = 14 nm. The stabilized |I VDD | depended on the applied V in (state of input). The magnitude of the stabilized |I VDD | for the input voltage of 0.5 V (state '1') was much higher than that for the other states, like the |I VDD | of the NTI and PTI shown in Fig. 3d. For an L G = 500 nm, a total P VDD of 6.37 nW was calculated by integrating V DD × |I VDD (t)| with respect to the 2 cycle time (2 T = 160 ns) and dividing it by the same time, i.e., (total P VDD ) = [V DD · 160 ns 0 ns |I VDD (t)|dt]/(160 ns). The TLD was evaluated in terms of τ d , P, and PDP. These values were semi-empirically extracted from the simulations, which were based on the fabricated device. Theoretically, τ d can be reduced by V th engineering by biasing the control gate, as well as by device down-scaling. The above three metrics were changed by reducing the gate length (L G ), as summarized in Table 1. As shown in Fig. 4d, the propagation delay times, t 1 from state '0' to state '1' and t 4 from state '2' to state '1' were longer than the other transition times (t 2 , t 3 , t 5 , and t 6 ) because I on, '1' is smaller than I on, '0' and I on, '2' . In this work, the τ d of TLD is predominantly governed by the longest transition time, t 1 (t 1 > t 4 ).   www.nature.com/scientificreports/ The possible operating frequency was calculated from f = 1 / (4τ d ) 34 . Following a constant field scaling scenario with a scaling factor of K (> 1), f in is proportional to K for the down-scaling 1 . Therefore, the f in for a short L G becomes f in ⋅long L G /short L G . For example, an f in of 12.5 MHz for an L G of 500 nm can be increased to 48.1 MHz with an L G of 130 nm. τ d was directly extracted and P was extracted for each f in predicted by the abovementioned scaling rule for an L G of 500 nm, 130 nm, 65 nm, 28 nm, and 14 nm, as shown in Table 1. The τ d of 5.57 ns for L G of 500 nm was drastically reduced to 0.085 ns for an L G of 14 nm. And the P of 6.37 nW for an L G of 500 nm was also reduced to that of 1.90 nW for L G of 14 nm. In addition, the PDP of 0.16 aJ was extracted from P of 1.9 nW and τ d of 0.085 ns for L G of 14 nm. The performance metrics of the proposed TLD are compared with the existing implementations, as shown in benchmarking Table 2 18,[35][36][37][38][39] .
The SS of the ICDG Si-NW MOSFET in this experiment was approximately 120 mV/dec, due to the poor interface quality of the TEOS used as the gate oxide. This can be decreased to sub-80 nm/dec replacing the thermally grown oxide or using a high-k dielectric material. Further improvement in the SS will additionally reduce τ d and P.
In this study, a ternary logic decoder (TLD) to allow the conversion from a ternary code to a binary code and vice versa has been demonstrated with independently controlled double-gate (ICDG) silicon-nanowire (Si-NW) MOSFETs. Feasibility of the TLD was explored by use of semi-empirical circuit-level simulations based on the measured device-level ICDG Si-NW MOSFET characteristics. Because the ICDG Si-NW MOSFET is not only suitable for a multi-V th scheme but also CMOS-compatible for mass-production, the proposed TLD would be a promising candidate to realize a MRS. Direct demonstration of the TLD with fully fabricated circuits is left as a further work. Circuit simulation for ternary logic decoder. Using the experimentally modeled devices, the operation, performance, and power consumption of the TLD were verified using the ATLAS mixed-mode TCAD simulations. To simulate the transient response of the TLD, V DD and V SS were set to 1 V and 0 V respectively. www.nature.com/scientificreports/