Threshold voltage instability and polyimide charging effects of LTPS TFTs for flexible displays

In this paper, we investigate the Vth shift of p-type LTPS TFTs fabricated on a polyimide (PI) and glass substrate considering charging phenomena. The Vth of the LTPS TFTs with a PI substrate positively shift after a bias temperature stress test. However, the Vth with a glass substrate rarely changed even with increasing stress. Such a positive Vth shift results from the negative charging of fluorine stemmed from the PI under the gate bias. In fact, the C–V characterization on the metal–insulator-metal capacitor reveals that charging at the SiO2/PI interface depends on the applied gate bias and the PI material, which agrees well with the TCAD simulation and SIMS analyses. As a result, the charging at the SiO2/PI interface contributes to the Vth shift of the LTPS TFTs leading to image sticking.


Scientific Reports
| (2021) 11:8387 | https://doi.org/10.1038/s41598-021-87950-0 www.nature.com/scientificreports/ increased from 2.08 × 10 -5 A to 2.46 × 10 -5 A, and field effect mobility increased from 85 to 113 cm −2 . However, under the identical stress conditions, the parameters of the LTPS TFT fabricated on glass substrate are rarely changed. It is somewhat interesting to note that the V th of p-type LTPS TFTs with a PI substrate is positively shifted under the negative gate bias. It is speculated that the negative charging is generated from the PI substrate below the gate insulation layer. In order to further probe the positive V th shifts, 4-pad evaluation was conducted. As shown in Fig. 2a, a bias of 50 V was applied to the floating gate adjacent to the LTPS TFT to minimize the effects of the poly channel on electrical charging in the PI substrate. V th behaviors are shown in Fig. 2b. As shown, the LTPS TFT with a glass substrate demonstrates stabilized V th behaviors throughout stressing at 70 °C up to 80,000 s. Note that Region I, II, and III represent the temperature and bias conditions used; 70 °C without bias, 70 °C with 50 V, and room temperature without bias, respectively. From Region I to II, the V th of the TFT with a PI substrate increases and positively shifts with increasing time. The V th tends to decrease and then return to the initial V th after 1 h in Region III. In turn, Region III is intended to observe the recovery behaviors of the V th of the LTPS TFT with a PI substrate. Since the recovery of the V th observed in Region III could result in display image disturbance, such as image sticking defined as residual images, efforts in electrical and physical characterization are inevitable. One would argue that the positive V th shifts of the TFT with a PI substrate mentioned are related to design flaws somehow associated with the layout design of the metal route, which can impact TFT stability as electrical fields arise from adjacent metals near TFT devices. However, such artifacts were eliminated by design review throughout circuit simulation.
Since the V th stability of TFT devices plays an important role for display image performance, particularly for image sticking, the relationship between the ΔV th vs. image sticking was investigated. Using the checkerboard test pattern, the image sticking index is estimated by comparing luminance changes before and after stressing 13 . The white area adjacent to black patterns in the checkerboard becomes darker after stressing, which indicates  www.nature.com/scientificreports/ image sticking. Figure 3 shows the correlation between PI charging induced ΔV th and image sticking. It is shown that the larger the ΔV th, the higher the propensity for image sticking. These results show that the correlation between V th shift and image sticking needs to be further discussed with electrical and physical characterization.

MIM capacitor fabrication, C-V measurement and physical SIMS characterization.
In an effort of probing the V th behaviors mentioned above, three different metal-insulator-metal (MIM) capacitors, such as Ag/PI/Ag, Ag/SiO 2 /Ag and Ag/SiO 2 /PI/Ag were prepared for the C-V measurements conducted by varying voltage at a frequency of 100 kHz. SIO 2 is the barrier layer of the LTPS TFT, and the thickness and process conditions are the same with the measured TFT. Figures 4a-d show the schematics of the vertical structure for the MIM capacitors, i.e., Ag/SiO 2 /Ag, Ag/PI/Ag, Ag/SiO 2 /PI/Ag, and the cross-sectional analysis of the MIM capacitor. An Ag metal electrode was sputtered onto the spin-coated PI and SiO 2 , deposited using the PECVD process. As a result, the PI and PI/SiO 2 function as the insulators between the metal electrodes. Using Eq. (1), the physical dimension, dielectric constant, and capacitance of each capacitor are estimated and summarized in Table 1. Figure 5 shows the results obtained from the C-V measurements. It is apparent that changes in capacitance depend on the MIM capacitors. The capacitances of the SiO 2 and PI dielectric insulators between the Ag (1)  www.nature.com/scientificreports/ electrodes rarely change, even with increasing voltage (see Fig. 5a,b). However, the capacitance of the SiO 2 /PI dielectric tends to increase with increasing voltage. It was also found that the magnitude of capacitance turns into the initial state after 1 h of halting bias, as shown in Fig. 5c. In Fig. 5d, the capacitance of the SiO 2 /PI rapidly increases with increasing voltage. Such results agree well with the recovery of the V th described in Fig. 2b. Thus, it is legitimate that the positive V th shift of a TFT with a PI substrate is attributed to charging between the SiO 2 and PI interface. As such, charge generation at the interface between the SiO 2 and the PI plays an important role for TFT device stability, particularly for the PI substrate. In sequence, SIMS analysis is adopted to explicate the positive V th shifts of p-type LTPS TFTs with a PI substrate. To understand the effects of PI on the V th shift, two different PIs with low and high crosslink density, named PI-A and PI-B, were chosen to prepare the Ag/SiO 2 /PI/Ag capacitor. We first suspected that oxygen or moisture had penetrated from the PI. Changes in hydrogen ions (H − ), hydroxyl group (OH − ), and oxygen ions (O − ) before/ after bias stress of Ag/SiO 2 /PI/Ag capacitors were confirmed through SIMS analysis. Figure 6 shows the results of SIMS analysis before and after bias stress of MIM capacitors fabricated based on PI-A and PI-B. There was no change in H − , OH − , or O − before/after bias stress, confirming that there was no penetration of oxygen or moisture from PIs. Figure 7 shows the correlation between the fluorine profile at the SiO 2 /PI interface and capacitance, characterized by SIMS and C-V measurement. Comparatively, the SIMS analyses revealed that PI-A has a higher florin content than PI-B at the interface (see Fig. 7a,c). In consequence, C-V measurements shown in Fig. 7b,d show that the capacitance of the MIM capacitor with PI-B is rarely changed even with increased stressing at 70 °C. It has been reported that the negative fluorine ions, F -, are subjected to transfer and trapped in the SiO 2 under the bias 14 . As a result, SIMS analyses evidences that a mobile ion Fin the SiO 2 /PI interface contributes to the positive shifts of LTPS TFTs with a PI substrate. This suggests that the amount of charging generated in the PI is dependent on the material property of the PI. Hence, the material property of the PI is a crucial factor that can influence LTPS TFTs with a PI substrate. It has been also found that PI charging that significantly affects TFT reliability can be successfully suppressed by the selection of a proper PI with high volume resistivity 15 . However, the charge generation and transfer into the barrier layer remained in unripe areas.  www.nature.com/scientificreports/ TCAD simulation for charge generation at the interface between the SiO 2 and PI. Based on empirical data collected from reliability assessments, Silvaco TCAD was used to simulate the effects of charging at the SiO 2 /PI interface on the TFT transfer curve. Figure 8 shows the I D -V G plot of an LTPS TFT with a PI substrate. As shown, the negative charging in the SiO 2 /PI interface shifts the V th to the positive direction, while the positive charging results in a negative V th shift. Accordingly, when − 2 × 10 11 /cm 2 charging is generated at the interface between the SiO 2 and the PI, the estimated V th shift toward the positive direction is 0.84 V. Table 2 contains the estimated TFT parameters, such as V th , μ FE , subthreshold swing (SS), and on/off ratio, based on the given charge injections shown in Fig. 8. Figure 9 is given to explain the hole concentration of an LTPS TFT with a PI substrate with the bias conditioned at V GS − 30 V and V DS − 0.1 V. The Reference (black filled circle) and − 2 × 10 11 /cm 2 (blue filled triangle) represent the LTPS TFT with and without charging at the SiO 2 and PI interface. Recall that 2 × 10 11 /cm 2 is obtained from the C-measurement summarized in Table 1. As shown in the inlet in Fig. 9, when the negative bias is applied to the gate of the LTPS TFT, hole carriers tend to be accumulated near the channel and then  www.nature.com/scientificreports/ exponentially decrease. However, when negative charging exists at the PI substrate, hole concentration decreases then increases below the channel depth of 30 nm. It is known that the negative charges at the interface between the SiO 2 and PI result in an early turn-on V th leading to increased field effective mobility and I on , which is similar to the I D -V G characteristic observed from the double gate TFTs 16,17 . Hence, the state of charging at the interface determines the characteristics of the LTPS TFTs with a PI substrate.

Conclusions
Considering the direction of V th shift of p-type LTPS TFTs with gate bias stress, the charge trapping mechanism, depending on the type of the substrate in the top gate structure, are comprehensively investigated. Unlike the glass substrate, the positive V th shift of p-type LTPS TFTs with a PI substrate under the BTS test results from the negative charging of fluorine at the interface between the SIO 2 and PI is proven by C-V measurement and SIMS characterization. In fact, the fluorine stems from the PI substrate under gate bias stress. Furthermore, TCAD simulation reveals that the direction of the V th shift strongly depends on the polarity of charge trapping at the SiO 2 and PI interface. The larger V th shifts are prone to the higher propensity of image sticking. Hence,

Methods
P-type LTPS TFTs were fabricated on either a PI or glass substrate through the standard backplane process, in which plasma enhanced chemical vapor deposition (PECVD) was used for a-Si and SiO 2 (barrier) deposition and crystallized into poly-Si by using excimer laser annealing (ELA). Thus, the vertical structure of the p-type LTPS TFTs consists of the gate/gate insulator/poly-Si/buffer/barrier/PI or glass substrate on the top gate structure. In a pixel circuit driver, 4/4 μm transistor and 200 μm/200 μm capacitance were monitored by I-V and C-V measurement. V th behaviors were monitored as a function of bias stress on the gates of the LTPS TFTs. To probe electrical charging in PI, three different metal-insulator-metal (MIM) capacitors, Ag/PI/Ag, Ag/SiO 2 /Ag, and Ag/SiO 2 /PI/Ag, were prepared for the C-V measurements. Changes in capacitance were measured as a function of voltage level. Moreover, the effects of charging in PI on the LTPS TFTs were taken into accounted by selecting different types of PIs such as PI-A and PI-B. Fluorine profiles were carefully analyzed by SIMS characterization. Finally, the effects of PI charging on the LTPS TFTs were consummated by using TCAD simulation.