Experimental validation of new self-voltage balanced 9L-ANPC inverter for photovoltaic applications

Multilevel inverters play an important role in extracting the power from renewable energy resources and delivering the output voltage with high quality to the load. This paper proposes a new single-stage switched capacitor nine-level inverter, which comprises an improved T-type inverter, auxiliary switch, and switched cell unit. The proposed topology effectively reduces the DC-link capacitor voltage and exhibits superior performance over recently switched-capacitor inverter topologies in terms of the number of power components and blocking voltage of the switches. A level-shifted multilevel pulse width modulation scheme with a modified triangular carrier wave is implemented to produce a high-quality stepped output voltage waveform with low switching frequency. The proposed nine-level inverter’s effectiveness, driven by the recommended modulation technique, is experimentally verified under varying load conditions. The power loss and efficiency for the proposed nine-level inverter are thoroughly discussed with different loads.


Proposed 9L-ANPC inverter
The proposed 9L switched-capacitor inverter topology is shown in Fig. 1. It comprises an improved T-type inverter, auxiliary switch, and switched cell (SC) unit. The improved T-type inverter consists of two dc-link capacitors (C 1 , C 2 ) connected in parallel with the input dc source (V in ), two unidirectional IGBT's with antiparallel diodes (S 1 , S 1 ′), and one bidirectional switch (B 1 ). The SC consists of two series-connected capacitors (C a and C b ), four unidirectional IGBT's with anti-parallel diodes (S 2 , S 2 ′, S 3 , and S 3 ′), and one bidirectional switch (B 2 ). The Auxiliary switch (S x ) is used to discharge the capacitors C a and C b during positive and negative half-cycles. The input voltage is shared among the dc-link capacitors C 1 and C 2 , in which V C1 = V C2 = V in /2 and V o = M × V in (M-modulation index, V o = V out ), balanced by the switch B 1 .
The capacitors C 1 and C 2 supply the dc voltage to the load during positive and negative half-cycle, respectively. The fundamental operation of proposed 9L inverter is given in Table 1.
As shown in Fig. 2 Figure 1. Proposed single-phase basic unit for 9L operation. Table 1. Fundamental operation of proposed 9L inverter.

Voltage balancing Voltage boosting
Since only two capacitors are connected in series with mid-point neutral connection. In zero state the switches B 1 is ON and provide the zero potential at point 'N' point Switched cell capacitors are rated to V in /4 In charging mode, the dc-link capacitor C 1 and C 2 is connected in parallel with C a and C b In discharging mode, the dc-link capacitor C 1 and C 2 is connected in series with C a and C b The auxiliary switch is used to connect the dc-link and FC in series The ratio of input to the output voltage is 1:1 in proposed 9L inverter During the parallel connection dc-link capacitor and FC, the FC is charging the voltage to V in /4   Fig. 2d. Hence, the negative half-cycle is obtained by choosing the corresponding switching path. During state 3 (± 3V in /4), capacitor C b discharges during the positive half-cycle and C a discharges during the negative half cycle. Mode 0 (0 V): The zero states are more essential to provide a freewheeling path to the load current when the load is inductive. The zero states are achieved either by turning on switches B 1 , S 2 , S 3 , D, D′ and S x or B 1 , D, D′, S x , S 2 ′ and S 3 ′ as shown in Fig. 2e,f. The proposed topology consists of two dc-link capacitors and two series-connected FCs. The FC voltages should be maintained to V in /4, but the dc-link capacitor voltages are V in /2. The output voltage (V out ) is obtained by using the switching functions, DC-link, and FC using Eq. (1): where the V C2 , V Ca and V Cb are the voltages of dc-link capacitor C 2 , floating capacitor C a and C b , respectively. The voltage across the dc-link capacitor and FCs are given in Eq. (2) The {1,0} is the logic values of the switching function, i.e., the switch is ON state it represents as "1" and for OFF state represent as "0", respectively. The corresponding switches are turned ON and OFF based on the given switching sequence in Table 2. The capacitance value of the FC depends on the ratio of charging and discharging time. Here, the FCs are charging and discharging is two times, but the duty cycle of charging is higher than the discharging, which means the proposed topology uses a lower number of dc capacitance. However, the current ratings are identical in all the switches. The maximum blocking voltage (MBV) on individual switches is obtained from Eqs. (1) TBV p·u = MBV S1,S1 ′ + MBV S3,S3 ′ ,S2,S2 ′ ,B1,Sx + MBV B2 , Table 2. Switching sequence of each level. C charging, D discharging, -no effect.

Mode
On-state switches Output voltage (V out )

Modified multicarrier triangular carrier signal
The conventional multicarrier PWM technique is used for low THD when the switching frequency is high. In order to reduce the switching frequency with reduced THD and high voltage RMS, a multicarrier level-shifted modulation scheme is introduced. The conventional carrier waveform under level-shifted multilevel pulse width modulation is decomposed into two intervals ranging from 0 to Ts/2 and Ts/2 to Ts with the amplitude of voltage varying from 0 to 1 and from 1 to 0 respectively in the mentioned time intervals as shown in Fig. 3a. To reduce the THDs and to increase the RMS value of the output voltage of the inverter, the proposed switching scheme under level-shifted multilevel pulse width modulation is subjected to a change in the amplitude of the carrier wave with the sampling time period of Ts equally divided into five intervals comprising of 0 to Ts/4, Ts/4 to Ts/2, Ts/2 to 3Ts/4 and 3Ts/4 to Ts. The amplitude in these intervals varies from 0 to 1, 1 to change in q (dq), dq to 1, and from 1 to 0, respectively, as illustrated in Fig. 3b. When dq = 0, the proposed scheme takes the shape of the conventional carrier waveform. When dq = 1, the proposed scheme modifies into the shape of an isosceles trapezoid. When dq = 1, a single pulse is generated in the time interval of Ts. This can further deteriorate the THD. Therefore, to mitigate this detrimental effect on THD, choosing the value of dq is of great significance. Figure 3c clearly shows the difference between the pulse width duration of the proposed carrier signal and the conventional triangular carrier signal. The optimal value of dq is chosen to be greater than 0 and lesser than 1. The generalized level-shifted carrier signal (V carr ) with sinusoidal reference signal (V Ref ) is represented in Fig. 4a and the typical 9L output voltage waveform is shown in Fig. 4b. The Eq. (9) gives the function f(x,y) of two level full bridge inverter is where m is the carrier index variable and n is the baseband index variable. The above equation consists of the fundamental component, and harmonics 15 . Since the proposed topology produces the double pulse when dq ≠ 1, and the Fourier equation can be further reduced and given in Eq. (10) where 'M' is modulation index. Since, the duty ratio of the proposed modulation scheme is higher than the conventional PWM, the proposed topology conduction time is high. Further as the switching angle of each pulses is different from that of the conventional PWM, leads to reduction of THD in proposed PWM technique as shown in Fig. 3c.

Determination of floating capacitors
The long discharging cycle (LDC) occurs for both the FCs during time interval (θ 3 − (π − θ 3 )). The maximum charge, required by the capacitor is given in (11) where, i L represents the load current. As θ 3 is obtained as in (12). Similarly, θ 4 can be obtained.
The maximum voltage ripple occurred at the resistive load. So, it is worth mentioning that the maximum discharge value for pure resistive load. Therefore, the ΔQ can be calculated as in (9) for capacitor C a and C b .
The ripple value (ΔV rip ) across the capacitor C a and C b is obtained (11) as R L is the resistive load and f f is the inverter output voltage frequency. The optimum value for each capacitor (C opt ) can be given as in (12).

Comparison of proposed multilevel inverter with other recent MLI topologies
A comparison of different switched capacitor MLI topology and conventional topologies are considered. In order to generate the 9L output voltage at the load, the CHB, NPC, and FC topologies use 16 switches; other than these, the NPC and FC need more clamping diodes, clamping capacitors, and additional dc-link balancing circuits. However, in the case of CHB, it needs four isolated dc sources and no voltage boosting. Apart from the conventional topologies, 10 developed a topology where eight switches and three diodes are used, but it requires four maximum blocking voltage (MBV) switches. The ratio of the input voltage versus the maximum blocking voltage is 1:4 (V in : MBV). Although the topologies in 6,8 are close to the proposed topology with the total standing voltage of 6 V in , these topologies do not have voltage boosting ability, unlike the proposed topology. The other parameters such as voltage rating of the capacitor (V C,rating ), the number of the capacitors (N Capacitors ), number of the diodes (N diode ) and number of sources (N source ) are compared and presented in Table 3 with recent 9L SCMLI topologies. Further, the recent topologies presented in 16,17 are compared with the proposed topology. In 16 , the topology does not have boosting ability and it is not an NPC type topology but the 17 is family of ANPC with high voltage gain with more number of switches. Further, the maximum blocking voltage is equal to the V out . However, from the Table 3, its confirming that the proposed topology is superior to the all-other topologies presented in the literature in terms of switch count.

Power loss analysis of the proposed topology
The losses in the power components occur due to non-idealities present with them. Three components compose the multilevel ANPC inverters' power losses are the switching losses, conduction losses of the power semiconductor devices, and ripple losses of the capacitors.
where P loss denotes the total power loss of the MLI with P c , P sw , and P ripple represents the switches losses, conduction losses and ripple losses, respectively. As a consequence of intrinsic delays in the switching of semiconductor components, during each switching transition overlaps between voltage and current leading to loss of switching which is calculated as where, V on is pre-ON state voltage across the power switch. I on is the current which flows through the power switch after the ON condition. T on is the period of transition in the ON state. V off , I off , and T off are the voltage across the power switch, current that flows through a power switch before the transition to OFF state and transition period of the OFF state, respectively. f f is the frequency of the fundamental output voltage. Conduction losses are power losses occurred due to the internal resistance offered by the switch during the conduction mode and is given as where I sw is the amount of current through a switch with an internal resistance of R on . Aside from power losses in the switch, the ripple losses, which occur due to the charging and discharge of the capacitors, are another major contributor to the overall power loss of the MLI. When the parallel capacitor to the dc source is charged, the charging current flows through the capacitor, and because of the difference in voltage between the input source and the capacitor voltage, the ripple voltage ΔV C causes the power loss. The ripple power loss of a capacitor can be calculated as Modeling the semiconductor devices in PLECS software has led to the power load distribution for the proposed topology. The efficiency of the proposed topology against the output power has been shown in Fig. 5. The proposed topology's maximum efficiency was measured at 200 W output power as 97.7%. The efficiency of the proposed topology is 94.1% at the output power of 2 kW. Even with higher output power, the proposed topology gives better efficiency, making it suitable for higher power applications. Table 4 shows the power loss of all switches and capacitors, together with the efficiency of the proposed topology with different loading combinations. Table 4 also shows the switching power loss (P sw ) and conduction power loss (P c ) of the devices with a ripple power loss of the capacitors. The maximum power loss occurs to the switch (16) P loss = P c + P sw + P ripple ,    www.nature.com/scientificreports/ pair (S 2 , S 2 ′) as these switches have to carry the charging current of the capacitors C a and C b . During charging the FCs, the charging current will be higher, leading to major losses in the devices and components. In Fig. 6, the dc-link capacitors have low power loss, but the FC losses are high (~ 16%), and the diodes presented in the mid-point of the dc-link capacitor also produce more losses because of the FC charging current. The bidirectional switch (B 1 ) can be replaced with two switches that may reduce the losses and increase efficiency. Nevertheless, the switch count and driver circuit will be added extra, leading to an increase in the inverter's cost. The sources of losses are switching the device and conduction loss during the ON time which is clearly cleared discussed in above section. Further, the other losses are: (i) DC link capacitor losses: These losses are mostly associate with capacitor voltage ripple and ESR value of the capacitors. Here, the ESR value of the capacitor is fixed by the manufacturer. (ii) Floating capacitor losses: The FC losses are high due to high charging current flowing in the charging loop. So, the FC capacitor leads to higher losses. However, in all the self-balanced switched capacitor topologies experiencing this loss. The voltage and current across each switch for one switching period is given in Fig. 7a,b. It is confirming that the maximum blocking voltage on switch is equal to the V in and the maximum current has occurred on the charging path devices.

Experimental results
The performance of the proposed 9L inverter is tested and verified in prototype hardware setup. The circuit diagram of proposed 9L inverter with PV applications for single and three phase system is shown in Fig. 8a,b. In hardware, the Xilinx Spartan 6 digital controller is used. The list of experimental parameters values is given in Table 5. In this V in is chosen as 200 V and output voltage is 200 V with unity gain. C 1 and C 2 capacitors are chosen as 1700 µF with low voltage ripple of 2% but in switched cell capacitors values are selected as 2700 µF based on the ripple voltage and switching frequency of the inverter as given in Eq. (15) and ΔV C is the ripple voltage of capacitor C a and C b , which range between 0.05 to 0.1 i.e., 5% to 10% variation and the f sw is switching frequency. The recommended modulation scheme is verified in experiments for a switching frequency of 2.5 kHz. Further to validate the proposed system for real-time applications, the prototype hardware model is fabricated. In hardware setup, the Semikron SKM75GB063D IGBT 600 V/75 A and TLP-250A gate driver circuits are used. The dead time of 4 µs is provided by using RC network. RL load is varied in the order of low-high-low to measure the adaptability of proposed inverter with respect to dynamic behavior and modulation under sudden load conditions as shown in Fig. 9a-g. In Fig. 9a the output voltage (M = 0.95 to 1.0) and current waveform for 10 Ω + 100 mH is presented with worst case of power factor is 0.3 and the simultaneously the dc-link capacitor and   Fig. 9b. Further, the load changes from 100 Ω, 50 mH to 10 Ω, 100 mH to confirm the suitability of proposed topology for any load variations as presented in Fig. 9c and load to no-load is shown in Fig. 9d. However, the load variations are limited based on the FC value. The maximum current through the switch is 6.0 A and the maximum blocking voltage is 200 V on S 1 and S 1 ′ switches. Another dynamic variation is modulation index changes from 0.8 to 1.0, and the V in changes from 100 to 200 V, as shown in Fig. 9f. In switched capacitor topology, the inrush current is another problem during the parallel connection of FC and input dc source. Due to inrush current need high current rated switches. In order to suppress the inrush current, the inductor is used in the loop, see the switch current and voltage in Fig. 9g.   www.nature.com/scientificreports/ Further, during the step input voltage changes the capacitors charging current is increasing suddenly and it reach to ~ 30A as shown in Fig. 9h. The experimental output power is 1210.7 W for high inductive load value and 380.4 W for highly resistive load with the efficiency of 94.4% and 97.7%, respectively. The proposed inverter operates less power loss and less costly due to the low number of power components and voltage rating on the switches. Further, the voltage THD of the proposed modulation scheme is compared with the conventional phase disposition (PD), phase opposite disposition (POD) and alternate POD, and parabola modulation scheme for different modulation index (M) as listed in Table 6. The proposed modulation scheme generates THD of 12.6% in experimental for switching frequency 2.5 kHz as shown in Fig. 10. The photograph of the experimental setup for the proposed topology is given Fig. 11. The details of each components and sensors are given in Table 7.

Conclusion
In this paper, a 9L-ANPC type topology and its operation have been presented. The proposed topology gain is equal to the V in , where 200 V is applied as input and 200 V is obtained at the output. The number of switch count is reduced with reduced FC voltage rating. The proposed topology is experimentally verified, and results are presented. The proposed topology is tested with a high inductive load value of 10 Ω/100 mH, which is approximately 0.3 power factor, and the proposed topology can generate the output voltage with 9L. Further, the loss values and power loss distribution for 100 Ω + 50 mH are presented, and 97.7% efficiency is achieved.
The experimental results concluded that the proposed topology has self-voltage balancing and voltage boosting ability. Further, this topology is suitable for PV applications.