Theory and experimental verification of configurable computing with stochastic memristors

The inevitable variability within electronic devices causes strict constraints on operation, reliability and scalability of the circuit design. However, when a compromise arises among the different performance metrics, area, time and energy, variability then loosens the tight requirements and allows for further savings in an alternative design scope. To that end, unconventional computing approaches are revived in the form of approximate computing, particularly tuned for resource-constrained mobile computing. In this paper, a proof-of-concept of the approximate computing paradigm using memristors is demonstrated. Stochastic memristors are used as the main building block of probabilistic logic gates. As will be shown in this paper, the stochasticity of memristors’ switching characteristics is tightly bound to the supply voltage and hence to power consumption. By scaling of the supply voltage to appropriate levels stochasticity gets increased. In order to guide the design process of approximate circuits based on memristors a realistic device model needs to be elaborated with explicit emphasis of the probabilistic switching behavior. Theoretical formulation, probabilistic analysis, and simulation of the underlying logic circuits and operations are introduced. Moreover, the expected output behavior is verified with the experimental measurements of valence change memory cells. Hence, it is shown how the precision of the output is varied for the sake of the attainable gains at different levels of available design metrics. This approach represents the first proposition along with physical verification and mapping to real devices that combines stochastic memristors into unconventional computing approaches.


Probabilistic Switching of VCM and ECM Cells
Pulse schemes for a) SET and b) RESET probabilities.First, an initial 1 ms (4 ms) long rectangular RESET (SET) of -1.4 V (1 V) is applied, which is followed by 0.1 V, 1 ms long READ pulse.The succeeding SET (RESET) pulse has variable amplitude and length.Finally, a 0.1 V, 1 ms long READ pulse is applied.
Success rates of 50 repetitions for each point for c) SET and d) RESET.
In Figure S1, the results of the measurements without sticking prevention are shown.It should be noticed, that the wanted dependency is mostly matched.Thus, a reduction in time while keeping the voltage constant results in a lower success rate.The same behavior is shown for a reduction of the voltage while keeping the timing constant.In the SET success rate are some discrepancies of the predicted behavior in the higher success rates.These could be due to the relatively small amount of repetitions or due to the high variability of the devices.In the measurements, it was observed that the initial resistance state showed a strong history dependence of the applied pulses.Thus, we introduced the unsticking preventions as shown in the main manuscript.For the success rate measurements, the difference in the two procedures appears at high voltages.In the case without unsticking preventions, a dip in the SET success rates is observed in the high voltage regime.
Figure S2 shows the probability of the switching for the SET and RESET process of the VCM cell at different voltages.It is obvious that a reduction of the pulse length would lead to a lower switching probability.Similar to the VCM cells, the switching kinetics of the ECM cells were investigated.The switching time was evaluated for all of the 50 cycles that switched successfully.The switching times are extracted in a similar way as for the VCM cells (see below).For the SET operation, the critical current level corresponds to a resistance of R crit = 1.5 kΩ.For extracting the RESET time, a critical current level of I crit,RESET = −140 µA at 0.22 V was chosen.Then, the absolute value of the critical current is reduced by 5 µA per 10 mV voltage increment (e.g.−130 µA at −0.2 V).The resulting switching time obeys an exponential relation on the applied voltage as shown for the VCM cells in Figure S3(a) and (b).The fitting equation are given in the figures.In Figure S3(c),(d), it is demonstrated that the SET/RESET switching times can be fitted using a Poisson distribution.
In Figure S4, the results of the ECM measurements are shown.As expected, the wanted dependency is mostly matched.A reduction of the voltage while keeping the timing constant First, an initial 1 s long rectangular RESET (SET) of -0.2 V (0.5 V) is applied, which is followed by 0.1 V, 1 ms long READ pulse.The succeeding SET (RESET) pulse has variable amplitude and length.Finally, a 0.1 V, 1 ms long READ pulse is applied.If the device did not switch and optional 1 s long SET (RESET) pulse of 0.5/,V (-0.2 V) is applied.

Success rates of 50 repetitions for each point for c) SET and d) RESET.
shows a lower success rate.The sticking problem was also present in the ECM devices since no current compliance or other protection mechanisms were used.Here the unsticking cycles were performed as non-triangular pulses and there is no additional cycling before the tested pulse.
The switching times (as shown in Fig. 3 of the main manuscript) for the VCM cells are extracted from the I-t traces recorded during the programming pulses.Figure S5 shows the transient currents for the SET and the RESET process for all cycles for a specific voltage.For both processes, a clear transition from one state to the other appears.The crossing point of the dashed lines with the I-t traces determines the switching time.For the SET operation, the critical current level corresponds to a resistance of R crit = 1.5 kΩ, i.e.I crit,SET = V pulse /R crit .This is the same condition as for defining the success rate from the Read pulse.The HRS, however, shows a nonlinear I − V characteristics, thus the large signal resistance at the pulse voltage will be lower than the read resistance.In addition, the RESET transition is more gradual in general.Thus, a different criterion

Measurement of the NAND Gate
In Figure S6, the results of the NAND gate measurements with unsticking cycles for all input combinations are depicted.The trends of the input combinations (p = '0'; q = '0'), (p = '1'; q = 6 '0') and (p = '1'; q = '1') of the theory are also visible in the measurements.Only the measurements of (p = '0'; q = '1') have a wrong trend.Here, the RESET of the second cycle is weaker (shorter pulse length and lower pulse height) than the initialization pulse of the SET measurements.Thus, the device will be in a lower ohmic HRS state than in the SET measurements and it will switch more easily back to the LRS state.

Probabilistic Analysis of CRS Logic Gates
In Figure S7, the probabilistic analysis for the logic gates in terms of the output probabilities and the corresponding accuracy is depicted.The gates form the basis for any logic operation and could be cascaded to have further arithmetic operations as well.100 simulation runs for each gate are conducted, and the resulting output is noted in regard to the expected output behavior for all the 8 entries in the truth table.The simulations showed a high level of matching with the analytical equations.
Figure S8 and S9 show the probabilistic analysis for the logic gates True, p, and q (Figure S8) and IMP, RIMP (Figure S9).As defined in the main manuscript the first initialization cycle is assumed to be deterministic.For the gates p, q, IMP and RIMP, the first cycle is identical to the True gate.Thus, the True gate is assumed to be deterministic to be consistent throughout the manuscript.
Figure S10 and S11 show the probabilistic analysis for the logic gates False, not p, and not q (Figure S10) and NIMP, RNIMP (Figure S11).As defined in the main manuscript the first initialization cycle is assumed to be deterministic.For the gates not p, not q, NIMP and RNIMP, the first cycle is identical to the False gate.Thus, the False gate is assumed to be deterministic to be consistent throughout the manuscript.

Derivation of the Accuracy of an XOR Gate
In order to derive the output probabilities of an XOR gate and its accuracy, it needs to be considered that the inputs of the second phase AND are non-deterministic anymore.They rather depend on the output probabilities of the NAND and the OR gate in the first phase of the XOR operation.It also needs to be considered that the output after the first phase is incorrect, but the final output after the second state can be correct.Thus, every case needs to be analyzed separately.First, we always need to derive the probabilities of the outputs of the first gate stage, i.e.P out,NAND (p,q) ('1'), P out,NAND (p,q) ('0'), P out,OR (p,q) ('1') and P out,OR (p,q) ('0').From this we can calculate the probability of the input combinations of the second stage, the AND gate, P in,AND (p.q) (x,y), where x and y denote the outputs of the NAND and the OR gate, respectively.These probabilities are multiplied with the probabilities of the AND gate to achieve the correct result of the XOR gate for the inputs p and q.
For the ease of readability P S is used instead of P S (t) in the following derivation.

Figure S1 :
Figure S1: VCM measurements without refresh cycles for different pulse lengths and heights.

Figure S2 :
Figure S2: Switching probability of the VCM cell for (a) SET and (b) RESET as a function of time.

Figure S3 :
Figure S3: The time-voltage relationship for the ECM device during the (a) SET operation and

Figure S4 :
Figure S4: ECM measurements with refresh cycles for different pulse heights.Pulse schemes for is chosen.Starting with a critical current level of I crit,RESET = −1.25 mA at -1.23 V, the absolute value of the critical current is reduced by 50 µA per 10 mV voltage increment (e.g.-1.2 mA at -1.22 V).

Figure S5 :
Figure S5: Exemplary I-t traces recorded during the programming of the VCM cell for the (a) SET

Figure S6 :
Figure S6: Comparison of the theoretical and measurement results of the NAND gate for the

Figure S7 :
Figure S7: The probabilistic analysis of logic gates with theoretical and simulation-based on be-

Figure S8 :
Figure S8: The probabilistic analysis of logic gates with theoretical and simulation-based on be-

Figure S10 :
Figure S10: The probabilistic analysis of logic gates with theoretical and simulation-based on