A three-terminal non-volatile ferroelectric switch with an insulator–metal transition channel

Ferroelectrics offer a promising material platform to realize energy-efficient non-volatile memory technology with the FeFET-based implementations being one of the most area-efficient ferroelectric memory architectures. However, the FeFET operation entails a fundamental trade-off between the read and the program operations. To overcome this trade-off, we propose in this work, a novel device concept, Mott-FeFET, that aims to replace the Silicon channel of the FeFET with VO2- a material that exhibits an electrically driven insulator–metal phase transition. The Mott-FeFET design, which demonstrates a (ferroelectric) polarization-dependent threshold voltage, enables the read current distinguishability (i.e., the ratio of current sensed when the Mott-FeFET is in state 1 and 0, respectively) to be independent of the program voltage. This enables the device to be programmed at low voltages without affecting the ability to sense/read the state of the device. Our work provides a pathway to realize low-voltage and energy-efficient non-volatile memory solutions.

IMT Without ferroelectric

S2. Electrically driven IMT in VO2 (Experimental characteristics)
Illustrative I-V characteristics showing electrically induced IMT and MIT in VO2 marked by an abrupt and hysteretic change in resistance. The device length and width was 10 µm. (mA)

S3. Nature of the electrical IMT in VO2
The origin of the IMT in VO2 has been the subject of intense research and debate 1 . Various models based on varying levels of contribution from a Mott-Hubbard type transition and a Peierlslike structural instability have been proposed to explain the transition. However, a comprehensive understanding of the exact origins of the IMT in VO2 still remains elusive. Consequently, this also implies that the exact mechanism of how an external stimulus such as an electric field affects the IMT in VO2 also remains to be completely understood.
Electronically driven IMT in VO2: Two-terminal VO2 devices exhibit an IMT when a voltage is applied across the VO2 channel. In this configuration, both electric-field and current-induced Joule heating effects are present 2 . While the exact origin of this transition is also disputed, there is increasing evidence of the preponderance of electro-thermal effects 3,4 . In a three-terminal device, a true gate-field induced IMT has not been demonstrated, although several useful features of the interaction between the (gate) electric-field and the VO2 channel have been revealed (we note that Nakano et al 5 . demonstrated a non-volatile phase transition using ionic liquid gating where the role of ionic diffusion and the electric field are challenging to deconvolute). A key feature of the application of an electric field (through the gate) on the VO2 channel is that it modulates the (threshold) voltage required at the source-drain to induce IMT 6 -a property that facilitates the design of the Mott FeFET proposed here. One possible explanation for this behavior is that even though the magnitude of the electric-field required to induce an IMT is significantly larger than that which can supported by a solid state dielectric, the field modulates the nucleation probability of the metallic phase (field induced nucleation) resulting in the change in the threshold voltage. We therefore propose a phenomenological model to emulate this behavior. V at their gate terminals. Therefore, the memory states of the HAR, HAC, UA cells remain undisturbed during both the write '0' (Fig. S4d), and the write '1' (Fig. S4e) operations.
Next, we discuss the distinguishability in the SL currents during the read operation. We utilize the difference in the SL currents to sense the memory states stored in the cells of an array. Fig. 4h in the main text shows the SL currents for the read operation of the memory cells in the second row.
It clearly shows that the SL currents provide sufficient distinguishability between logic '0' and logic '1' states. For sensing, a current sense amplifier (CSA) is connected to each SL, as shown in Fig.   S4a. Figure S4b shows the schematic of the CSA 8 that we have used in this work. The reference current (IREF= 10 A) is appropriately chosen to obtain different binary outputs (0 and VDD) for logic '0' and logic '1', respectively. Figure S4c shows the SL currents and corresponding logic outputs of the CSA during the read operation.