Electric-double-layer p–i–n junctions in WSe2

While p–n homojunctions in two-dimensional transition metal dichalcogenide materials have been widely reported, few show an ideality factor that is constant over more than a decade in current. In this paper, electric double layer p–i–n junctions in WSe2 are shown with substantially constant ideality factors (2–3) over more than 3 orders of magnitude in current. These lateral junctions use the solid polymer, polyethylene oxide: cesium perchlorate (PEO:CsClO4), to induce degenerate electron and hole carrier densities at the device contacts to form the junction. These high carrier densities aid in reducing the contact resistance and enable the exponential current dependence on voltage to be measured at higher currents than prior reports. Transport measurements of these WSe2 p–i–n homojunctions in combination with COMSOL multiphysics simulations are used to quantify the ion distributions, the semiconductor charge distributions, and the simulated band diagram of these junctions, to allow applications to be more clearly considered.


Results and discussion
Schematic cross sections for two p-i-n junctions are shown in Fig. 1a,b, respectively, in two different channel structures. Following the benchmarking of Sylvia 24 for ultrascaled field-effect transistors (FETs), we focus on WSe 2 as the channel material. Device D1 has a centered top gate with an Al 2 O 3 thickness of 5.3 nm and device D2 has an open channel. Fabrication details are provided in the Methods section. The upper layer is the solid polymer electrolyte, PEO:CsClO 4 . The CsClO 4 dissociates into cations, Cs + , and anions, ClO 4 − , as indicated by the circled + and − symbols in Fig. 1a,b. The metal contact to WSe 2 consists of an electron beam deposition of Ti to partially cover the exfoliated WSe 2 surface followed by Pd deposition. This leads to a dual work-function contact providing low Schottky barriers to both valence and conduction bands 18 . With a positive bias applied to the right contact with respect to the left contact, ions accumulate at the contacts as indicated in the schematic with the bulk of the PEO:CsClO 4 remaining charge neutral. An EDL forms where the ions accumulate. Shown in Fig. 1c,d are transmission electron microscope (TEM) images of the contact region made after electrical measurements were completed. An interfacial layer at the scale of approximately 1 nm can be seen at the metal contact/WSe 2 interface. This contact is formed by partially covering the WSe 2 with Ti and then completing the metallization with Pd. For this reason, some transition layer can be expected. This dual work-function contact yielded contact resistances as low as 1 and 3.4 kΩ μm for n and p type contacts, respectively, comparable to the best reports for WSe 2 18 . The physical attributes of the two devices are summarized in Table 1. To form the p-i-n junction, a positive bias is applied to the drain contact and a negative bias of the same magnitude is applied to the source contact, at room temperature. This accumulates negative ions at the drain contact and positive ions at the source contact, Fig. 1a,b. The ions then induce free carriers in the WSe 2 of opposite sign, i.e. electrons at the source and holes at the drain. The structure D1 enforces an undoped region in the center of the channel because the top gate keeps ions out of the central channel region, while the open structure D2 has a central undoped channel due to the charge neutral electrolyte in the region between the electrodes. Once the ions are positioned along the channel, they are locked into place by cooling the device below the glass transition temperature of the PEO:CsClO 4 (measured by Xu 7 to be 240 K) while maintaining the biases on the contacts. Below the glass transition temperature, the ions are immobilized and do not respond to external biases and the device can be tested without ion reconfiguration.    www.nature.com/scientificreports/ The transfer characteristic of the p-i-n diodes, D1 and D2, are shown in Fig. 2a,b, respectively. The I-V characteristics show a clear rectifying behavior with a forward to reverse current ratio of ~ 28,000 for D1 and ~ 2,000 for D2. More notable is the exponential dependence of the current on voltage over more than 4 orders of magnitude in both device geometries. The p-i-n junction is in series with metal/WSe 2 Schottky contacts with an n-Schottky barrier on the left contact and a p-Schottky barrier on the right, Fig. 2a inset. Under forward bias, the two Schottky contacts are reverse-biased tunnel contacts resulting from the degenerate n and p carrier densities of the EDLs near the contact/channel edges. This series arrangement of Schottky barrier contacts means that the voltage across the junction will be somewhat less than the applied voltage.
The current in the forward-biased p-n junction, I = I O exp[V/ηV T ], is predominantly controlled by the exponential factor V/ηV T where V is the voltage across the p-n junction, V T is the thermal voltage, V T = kT/q, η is ideality factor, I O is reverse saturation current, k is Boltzmann's constant, T is temperature, and q is fundamental charge. The ideality factor of D1 and D2 can be extracted from the forward biased I-V characteristic using η = [(kT/q)ln(10)(dlog(I)/dV)] −1 , which is valid when the applied voltage is predominantly dropped across the p-n junction. Figure 2c compares the ideality factor vs. current in D1 and D2 vs. published TMD p-n homojunctions. In Zhang 10 and Sutar 5 the width of the MoS 2 junction was not specified and 4 μm is used. Choi's 12 report, on MoS 2 using chemical doping, is an example where the ideality factor varies strongly with current, which is likely due to a series resistance. Sutar 5 formed the p-i-n junction in MoS 2 electrostatically by applying asymmetric biases to buried gates. The ideality factor in Sutar's report is constant over 4 orders of magnitude in current with ideality less than approximately 2. The p-i-n junctions that extend to the highest currents in Fig. 2c were created by the formation of EDLs. Among these reports, Zhang 1011 used ionic liquids, while in the junctions of Xu 7 and this work, PEO:CsClO 4 was used. The WSe 2 p-i-n junctions of this work exhibit substantially constant ideality factor vs. current, over 3 orders of magnitude; these lateral junctions show ideality factors ranging from 2 to 3. In contrast, the transferred MoSe 2 homojunction of Jin 15 exhibited nearly unity ideality, suggesting that trap-mediated generation/recombination 25 is playing a role in lateral junctions. In the lateral p-i-n junction, the reverse leakage is also higher than the reverse saturation current, consistent with traps playing a significant role.
While it may appear that the D2 junction has a larger temperature dependence than D1, this is only because the measured temperature range is larger for D2. The temperature coefficient, ΔI/ΔT of the forward current is similar in the two junctions 1.4 (nA/μm)/K in D1 and 1.1 (nA/μm)/K in D2 (at 10 nA, normalized by the junction width W). The positive temperature coefficient in forward bias is opposite to what is expected from the exp(qV/kT) factor at fixed voltage. This is because the prefactor, I O , depends on the energy band gap, E G , making the full forward current proportional to exp[− (E G − qV)/kT] as outlined by Sze 26 , and giving a positive temperature coefficient.
The temperature coefficient of the Schottky contacts and access region can be separated out in the same device. To facilitate this, device D2 was cooled to below the glass transition temperature of PEO, with a 2.5 V side gate bias and 0 V on the source and drain contacts. Thus, positive Cs + ions are driven onto the WSe 2 surface, as indicated in Fig. 3a, to induce electrons in the channel, as described in the band diagram in Fig. 3b. Nonrectifying I-V characteristic were obtained as a result of this unipolar doping, Fig. 3c, and the temperature coefficient of the current is weakly negative.
A negative temperature coefficient is not readily explained from Schottky barrier transport, considering Schottky barrier lowering 27 and thermionic field-emission 28 . A negative temperature coefficient is instead an indication of mobility degradation with temperature due to phonon scattering, as is also observed in Si metal-oxide-semiconductor FET inversion layers 29 . A negative temperature coefficient of the conductance has also been observed in WSe 2 FETs using PEO:CsClO 4 8 . The measured series resistance can be directly measured from Fig. 3c in the linear region below 1 V, where 8.7 kΩ is obtained, corresponding to a channel resistivity www.nature.com/scientificreports/ of 6.5 mΩ cm, which is reasonable for WSe 2 mobility and sheet carrier density (100 cm 2 /Vs and 6 × 10 12 /cm 2 ). Because both the p-i-n junction current and the series resistance increase with temperature, the voltage drop across the p-i-n junction decreases with temperature. COMSOL multiphysics simulations were performed to better understand the EDL junction formation. Given that this junction formation method is yielding the most ideal and high current homojunctions it is of interest to quantify the expected carrier densities and profiles. Figure 4a represents the simulated device structure for device D2, consisting of a 100 nm-long, 6.5 nm-thick WSe 2 channel (E G = 1.  31 . This simple assessment reveals that the portion of the channel strongly affected by the presence of ions is mainly in close proximity to the source and drain contacts, hence it justifies our choice to simulate a scaled version of the fabricated device. The Al 2 O 3 central gate in device D1 plays an insignificant role in the transport as the p-i-n junction is controlled by the high carrier density regions located within ~ 20 nm of the contacts. This is why devices D1 and D2 produce similar characteristics. The stabilized ion doping profile forms a p-i-n junction in the polymer, and the resulting net ion distribution mirrors the same junction at the surface of the underlying semiconductor channel. With the computed steady-state room-temperature ion distribution, Poisson's equation is then solved at 220 K under zero bias conditions using the net ion concentration as a fixed charge input. The accumulated anions (cations) near the drain (source) contact induce holes (electrons) in the underlying semiconductor layer. The equilibrium band diagram (V DS = V BG = 0 V) in Fig. 4c clearly shows that a barrier is formed due to the ionseparation, which is confirmed by the free carrier accumulation near the two ends of the semiconductor up to degenerate levels as shown in Fig. 4d. The band diagram also shows a graded profile due to the exponential decay in free carrier density. The graded profile reduces the abruptness of the junction profile, which is limited by the channel length linking the two highly-doped regions. The asymmetry in the hole and electron profiles www.nature.com/scientificreports/ is a consequence of the Schottky barriers at the metal contacts and the metal-oxide-semiconductor structure leading to a slight background accumulation of holes in the channel (~ 10 13 cm −3 ). The carrier density slopes, 2.4 nm/decade for electrons and 4.1 nm/decade for holes, are highly abrupt relative to impurity dopant slopes, which are larger by a factor of two or more 32 .

conclusions
Lateral EDL WSe 2 p-i-n junctions are demonstrated with substantially constant ideality factors over nearly 4 orders of magnitude using PEO:CsClO 4 to accumulate electrons and holes at the channel contacts. The high carrier densities at the contacts lead to a low resistance of the Schottky barriers and a series resistance which is dominated by the channel access resistance. The lower series resistance of these structures enables observation of the exponential dependence of the forward current over a wider range than previous studies. COMSOL simulations reveal that degenerate carrier densities are induced with abrupt carrier profiles in the vicinity of the contacts. The junction formation method of this paper using PEO:CsClO 4 and without a side gate achieves the highest currents with most ideal rectification properties reported to date in doping homojunctions in 2D materials.
In considering applications of this junction formation method, the requirement that the ions need to be positioned under bias and cooled to freeze them in place is undesirable and likely impractical. This freezing www.nature.com/scientificreports/ requirement can be lifted if a polymer with a higher glass transition temperature is used, as discussed by Kinder 33 , or if the EDL-induced junction can be frozen in place at room temperature via crosslinking using a thermally triggered polymerization, as demonstrated by Liang 34 . Another way to eliminate the need to freeze the ions in place is to make the ion positioning bias and the operating bias the same; in this case cooling is not required as the fixed forward bias holds the ions in place. This is used, for example, in p-i-n junctions formed by this technique and used as light-emitters 1920 . However, if the terminal biases change, the ions will re-equilibrate and the emission characteristics can be expected to change accordingly. Another question for this technology is scalability. There exist reports of carbon nanotubes (CNTs) with diameter of 2 nm coated and controllably electrolytically gated with PEO:LiClO 4 35 , showing that there is no intrinsic limit to coating cylindrical structures at the 2 nm scale. InAs nanowires with 50 nm diameter have also been successfully coated and gated with PEO:LiClO 4 36 . The electrolyte itself can also be scaled; ultrathin films of PEO have been spin coated down to 8 nm thickness, and exhibit well-behaved electrical properties 37 . However, to our knowledge there is no investigation of the viability of this doping method in highly-scaled VLSI (very large scale integration) geometries. Regarding the scaling of the TMD thickness, there are no fundamental impediments to the junction formation approach at the single monolayer thickness.

Methods
Devices D1 and D2 were fabricated in separate process runs. The fabrication began with backside evaporation of Ti/Au (5/100 nm) on the unpolished side of a p + Si wafer. Next, 27 nm of Al 2 O 3 was deposited on the Si top surface by atomic layer deposition (ALD). Synthesized WSe 2 flakes (from 2D Semiconductors Co. with 99.9995% purity) were exfoliated on the oxide using dicing tape (Semiconductor Equipment Corp. P/N 18074). The flakes were patterned for source and drain using electron beam lithography (EBL) followed by metal deposition of Ti/Pd (0.8 nm/90 nm) and lift off. Device D1 omitted the gate process. Device D2 used a TiOPc adhesion layer following by the ALD process of Park and Fathipour 38 . Finally, the top gate contacts were patterned using EBL, followed by thermal metal deposition of 90 nm Pd and lift off. The oxide was then etched from the access regions of the FET in buffered HF, using the top gate as an etch mask. The device structures of this paper were fabricated in the same process run reported in reference 18 ; in that paper the transistor and contact properties were analyzed using side-gates to position the ions. In this paper we focus on the formation of p-i-n junctions in transistor geometries without the use of auxiliary gates.
The solid-polymer electrolyte preparation and materials have been previously detailed 18 . In short, PEO (95,000 g/mol) and CsClO 4 were dissolved in anhydrous acetonitrile at a concentration of 1 wt%, and an ether oxygen to Cs + molar ratio of 168:1. The solution was drop-cast in an Ar-filled glove box, < 0.1 ppm O 2 and H 2 O, and then annealed for 3 min at 90 °C. Current-voltage measurements were made in a Cascade Microtech PLC50 vacuum probe station at 1.2 × 10 -6 Torr. Devices that employ PEO:CsClO 4 are stable and give reproducible electrical characteristics under testing over months, as long as the applied voltages are kept within the electrochemical window of the electrolyte (± 4 V) and wafers are stored between testing in an Ar or vacuum ambient to prevent water absorption of the PEO.