Experimental Demonstration of Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses

Spiking neural networks (SNN) are computational models inspired by the brain’s ability to naturally encode and process information in the time domain. The added temporal dimension is believed to render them more computationally efficient than the conventional artificial neural networks, though their full computational capabilities are yet to be explored. Recently, in-memory computing architectures based on non-volatile memory crossbar arrays have shown great promise to implement parallel computations in artificial and spiking neural networks. In this work, we evaluate the feasibility to realize high-performance event-driven in-situ supervised learning systems using nanoscale and stochastic analog memory synapses. For the first time, the potential of analog memory synapses to generate precisely timed spikes in SNNs is experimentally demonstrated. The experiment targets applications which directly integrates spike encoded signals generated from bio-mimetic sensors with in-memory computing based learning systems to generate precisely timed control signal spikes for neuromorphic actuators. More than 170,000 phase-change memory (PCM) based synapses from our prototype chip were trained based on an event-driven learning rule, to generate spike patterns with more than 85% of the spikes within a 25 ms tolerance interval in a 1250 ms long spike pattern. We observe that the accuracy is mainly limited by the imprecision related to device programming and temporal drift of conductance values. We show that an array level scaling scheme can significantly improve the retention of the trained SNN states in the presence of conductance drift in the PCM. Combining the computational potential of supervised SNNs with the parallel compute power of in-memory computing, this work paves the way for next-generation of efficient brain-inspired systems.

Spiking neural networks (SNN) are artificial computational models that have been inspired by the brain's ability to naturally encode and process information in the time domain.The added temporal dimension is believed to render them more computationally efficient than the conventional artificial neural networks, though their full computational capabilities are yet to be explored.Recently, computational memory architectures based on non-volatile memory crossbar arrays have shown great promise to implement parallel computations in artificial and spiking neural networks.In this work, we experimentally demonstrate for the first time, the feasibility to realize high-performance event-driven in-situ supervised learning systems using nanoscale and stochastic phase-change synapses.Our SNN is trained to recognize audio signals of alphabets encoded using spikes in the time domain and to generate spike trains at precise time instances to represent the pixel intensities of their corresponding images.Moreover, with a statistical model capturing the experimental behavior of the devices, we investigate architectural and systems-level solutions for improving the training and inference performance of our computational memory-based system.Combining the computational potential of supervised SNNs with the parallel compute power of computational memory, the work paves the way for next-generation of efficient brain-inspired systems.
In recent years, deep learning algorithms have become successful in solving complex cognitive tasks surpassing the performance achievable by traditional algorithmic approaches, and in some cases, even expert humans.However, conventional computing architectures are confronted with several challenges while implementing the multi-layered artificial neural networks (ANNs) used in these algorithms, especially when compared against the approximately 20 W power budget of the human brain.The inefficiencies in the von Neumann architecture for neural network implementation arise from the high-precision digital representation of the network parameters, constant shuttling of large amounts of data between processor and memory, and the ensuing limited computational parallelism and scalability.In contrast, the human brain employs billions of neurons that communicate with each other in a parallel fashion, through dedicated, analog, and low-precision synaptic connections.The spike-based data encoding schemes used in these biological networks render the computation and communication asynchronous, event-driven, and sparse, contributing to the high computational efficiency of the brain.
The size and complexity of artificial neural networks are expected to continue to grow in the future and has motivated the search for efficient and scalable hadware implementation schemes for learning systems 1 .Spiking neural networks (SNNs) are excellent candidates to implement large learning networks, especially for energy and memory-constrained embedded applications, as they closely mimic some of the key computational principles of the brain.Application specific integrated circuit (ASIC) designs such as TrueNorth from IBM 2 and Loihi from Intel 3 , that implement SNN dynamics, have been successful in demonstrating two to three orders of magnitude energy efficiency gain by mimicking the sparse, asynchronous, and event-driven nature of computation in the brain.However, the area expensive static random access memory (SRAM) circuits used for synaptic weight storage in these chips limit the amount of memory that can be integrated on-chip and hence the scalability of these architectures.
Crossbar arrays of analog non-volatile memory devices can perform weighted summation of its word line voltages in parallel using the device conductances and the results are available as currents at its bit lines.This memory architecture performing computations (computational memory) is using a combination of Ohm's law and Kirchhoff's law to reduce matrix-vector multiplications to O(1) complex operations [4][5][6][7] .Neural networks have layers of neurons each of which receive a weighted summation of neuronal response from its previous layer.The underlying matrix-vector multiplications are computationally expensive in traditional digital systems due to their large sizes and the necessity to store these matrices off chip.SNNs processing asynchronous events in time can significantly benefit from an on-chip computational memory that could store the synaptic weights in the device conductance values and provide dedicated connectivity patterns to process parallel events in real-time (Fig. 1a).For instance, such computational memory based SNNs could also be directly interfaced with spike encoding sensors such as artificial retina 8 or cochlea 9 to process asynchronous binary spike streams of real-world signals.
a) Electronic mail: ase@zurich.ibm.comb) Electronic mail: bipin@njit.eduThe synaptic conductance changes measured using changes in excitatory postsynaptic current (EPSC) as a function of its initial EPSC amplitudes, from the hippocampal neurons in a rat 10 .The state-dependent nature of conductance change in response to positive (causal) spiking is analogous to that observed in the PCM devices.

Neurons
However, achieving software-equivalent performance using computational memory realized using today's memory devices is challenging, due to the inherent non-idealities in the conductance modulation characteristics of these nanoscale devices.Phasechange memory (PCM) is a mature non-volatile memory technology that has demonstrated gradual conductance modulation, however it exhibits several non-ideal characteristics that are typical to most nanoscale memories, including limited precision, stochasticity, non-linearity, as well as drift of the programmed conductance states with time 11,12 .Nonetheless, large-scale experiments demonstrating the effective use of PCM as synapses in ANNs show significant promise 11,13 .PCM is an attractive technology also for SNN implementations 12,[14][15][16][17] and the similarity of the state-dependent nature of the conductance update in PCM and in a biological synapse (Fig. 1b, c) opens up the possibility of exploiting the device physics rather than merely being limited by them.Most of the research efforts and experimental demonstrations using PCM in SNNs focus on an unsupervised training based on a local learning rule observed in biology known as spike-timing-dependent plasticity (STDP) 10 .However, unsupervised STDP based learning generally yields sub-par results in comparison to supervised training or has been limited to problems where the desired response of the neural network is not known beforehand 18 .There is also a growing body of evidence from neuroscience literature suggesting that data encoding using precise spike times in biological neural networks [19][20][21] have several computational advantages compared to rate based encoding schemes 22 .
In this article, we focus on in-situ supervised training of SNNs that learn to generate spikes that encode data corresponding to real-world signals using precise spike times and experimentally demonstrate their hardware implementation using more than 177,000 on-chip PCM devices.Moreover, we capture the statistical behavior of PCM devices with accurate models and use them to evaluate the improvement in training performance as a function of the number of PCM devices used per synapse.Next, we examine how modifications to the input encoding scheme with random jitter can improve learning and lastly, we demonstrate an array-level compensation scheme to tackle the accuracy drop due to temporal evolution of PCM-based synapses.The audio signal is passed through a silicon cochlea chip to generate spike streams.These spike streams are sub-sampled and applied as input to train the single layer SNN.The desired spike response from the networks representing the images (14 × 12 pixels) corresponding to the characters in the audio is also shown.
The training problem and the network we used for the experiment are illustrated in Fig. 2. The learning task of the network is to recognize and translate audio signals corresponding to spoken alphabets into corresponding images, with all information encoded in the spike domain, as described below.An audio signal captured when a human speaker utters the characters 'IBM' (Eye..Bee..Em) is converted to a set of spike streams using a Silicon cochlea chip 9 and the resulting 132 spike streams (representing the signal components in 64 frequency bands) are subsampled to an average spike rate of 10 Hz to generate the binary spike inputs to the network (see Methods for more details).A raster plot of the generated spikes is shown in Fig. 2. At the output of the network, there are 168 spiking neurons, with the spike in each neuron representing the instantaneous pixel intensity of the image corresponding to the input audio signal.The desired spike stream from each output neuron is obtained from a Poisson random process whose arrival rate is chosen to be proportional to the corresponding pixel intensities in the images (14×12 pixels showing the characters 'I', 'B', and 'M'), inspired by similar statistical distributions observed in animal retina 21 .Each image has an average duration of 230 ms and is mapped to the corresponding time window in the audio signal.The network hence receives 132 spike streams corresponding to the audio signals and is connected to 168 spiking neurons at the output, corresponding to the pixels of the image.In the experiment, the synaptic strength between the input streams and the output neurons is represented using the conductance of the PCM devices.
An input spike, arriving at time t i on an input synapse, triggers a current flow into the output neuron.The synaptic current in response to each spike is modeled as I ker (t) = (e −(t−t i )/τ 1 − e −(t−t i )/τ 2 )u(t − t i ) multiplied by synaptic weight W , where u(t) is the Heaviside step function (with τ 1 = 5 ms and τ 2 = 1.25 ms).The sum of all the weighted currents are integrated by leakyintegrate and fire (LIF) neurons to determine a voltage analogous to the membrane potential of the biological neurons.When this voltage exceeds a threshold, it is reset to a resting potential and a spike is assumed to be generated.During the course of training, PCM conductance values read from hardware are used to calculate the synaptic currents and the neuronal dynamics are implemented in software.A supervised training algorithm is used to determine the desired weight updates such that the observed spikes from the SNN are at the desired time instances.The weight updates will be implemented by modulating the corresponding PCM conductance values by applying a sequence of programming pulses.We avoid verifying if the observed conductance change matches the desired update.This blind programming scheme (without expensive read-verify) is expected to be the norm of computational memory based learning systems in the future and in this study we experimentally evaluate the potential of analog PCM conductance to precisely encode spike time information in SNNs.

B. Phase-change memory synapse
For our on-chip training experiment, we used a prototype chip containing more than one million doped-Ge 2 Sb 2 Te 5 (GST) based PCM devices fabricated in 90 nm CMOS technology node 23 .The GST dielectric has a lower resistivity in its polycrystalline state and a high resistivity in its amorphous phase.An amorphous region is created around the narrow bottom electrode via a melt-quench process.Its conductance can be gradually increased by a sequence of partial-SET pulses applied to the device.A threshold switching phenomenon permits large current flowing though the amorphous volume to increase its temperature and to initiate crystal growth.We have characterized the crystal growth driven conductance evolution in the PCM array and have created statistically accurate models 24 .The PCM models are used to pre-validate the experiment and to evaluate methods to improve training performance.
While the conductance increment (SET) operation in PCM can be gradual and accumulative, the melt-quench driven conductance decrement (RESET) process is non-accumulative.This leads to an asymmetric update behavior in conductance increase and decrease, necessitating the use of the standard differential configuration for weight updates 25 .In this scheme, each network weight W is realized as the difference of two PCM conductance values G p and G n (W = β (G p − G n ) where β is a scaling factor to be implemented in the peripheral circuit of the computational memory array).This allows both increment and decrement of the W to be implemented as partial-SET operations on G p and G n , respectively.This differential configuration improves the symmetry of weight updates and partially compensates the conductance drift 26 .Further improvement in conductance change granularity, stochasticity, and drift behavior can be achieved via a multi-PCM configuration 12,27 .In our training experiment, both the G p and G n are realized as the sum of four PCM devices.For each synaptic update desired by the training algorithm, only one of the four devices is programmed, chosen cyclically so that on average all devices receive approximately equal number of update pulses 12 .The energy overhead from the multiple devices per synapse is not expected to be significant since PCM devices can be read with low energy (1 -100 fJ per device) 28 and only one of the devices is programmed per update as in a conventional synapse.Although we are increasing the area for each synapse, it is worth noting that typical computational memory based design area for neural networks are dominated by the circuits for peripheral neurons rather than the synapse.Moreover, PCM devices have been shown to scale to nanoscale dimensions 29 and through technology scaling, the synaptic area could reduce significantly 30 .Thus in our implementation, each synapse is realized using 8 PCM devices, making a total of 177,408 devices to represent the weights of 22,176 synapses in the network.

C. Training algorithm
The supervised training of SNNs is a challenging task as the gradient descent based backpropagation algorithms do not apply directly due to the non-differentiable dynamical behavior of spiking neurons (i.e., the membrane potential encounters a discontinuity at the point of spike).One approach to circumvent this limitation is to train a continuous-valued ANN using standard backpropagation algorithm and then convert it into a SNN [31][32][33] .However, in this method, the input data and neuron activations in the ANN are translated to spike rates in the SNN, losing the advantage of precise time-based signal encoding, and necessitating longer processing times leading to sub-par performance and energy efficiency 34 .Also, the unconstrained training of the floating point synapses without taking into account the non-idealities of analog memory devices will lead to further loss in accuracy when the the trained weights are transferred to nanoscale synapses in hardware.Moreover, training approaches that implement back-propagation in SNNs using approximate derivatives of the membrane potential around the time of spikes are also aimed at minimizing cost functions, which have been described in terms of the output spike rate rather than precise spike times 35,36 .Encoding events using precise spike times could be more efficient as it leads to sparse computations and low latencies for decision making 2, [37][38][39][40] .
Recently, several approximate spike time based supervised training algorithms have been proposed of varying computational complexity that have demonstrated various degrees of success in benchmark problems in machine learning.Among these, SpikeProp 37 is designed to generate single spikes, Tempotron 39 uses a non-event driven error computation, and ReSuMe 41 and NormAD 42 (with relatively higher convergence rate) are designed to generate spikes at precise time instances via spike driven weight updates.In our experiment, we use the normalized approximate descent (NormAD) algorithm which has been successful in achieving high classification accuracy for the MNIST hand-written digit recognition problem 43 .According to this algorithm, the weight updates ∆W are computed in an event-driven manner, using the relation where η is the learning rate, T is the pattern duration, and e(t) is the difference between desired and observed binary spike trains.First, we used the PCM model to pre-validate and optimize the training scheme.Fig. 3a shows the improvement in network training accuracy as the number of PCM devices used per synapse increases (in differential configuration).The performance of the network is evaluated using an accuracy metric defined as the percentage of the number of spikes out of a total of 987 in the desired pattern which have an observed spike from the SNN within a certain time interval.In the line plot of accuracy with shaded bounds, the lower bound, middle line, and the upper bound respectively correspond to spike time tolerance intervals of 5 ms, 10 ms and 25 ms.Note that the average output spike rate for each of the character duration was less than 20 Hz corresponding to an inter-arrival time of 50 ms, and the task of the network is to create spikes each one of which can be unambiguously associated with one of the target spikes.A fixed weight range obtained from the reference high-precision training was mapped to the sum of conductance of 1 to 16 differential pairs and networks were trained for 100 epochs.Using more number of devices in parallel, with only one programmed at each weight update, permitted smaller weight updates to be programmed more reliably.Although the accuracy was found to improve with more PCM devices, increasing the total number of devices beyond 16 in this problem did not lead to corresponding improvements in accuracy.One possible explanation is that, with more number of devices the observed conductance change (which has a limited dynamic range for a chosen partial-SET programming scheme) captures smaller desired weight changes but neglects the larger desired weight changes, leading to slower convergence.The maximum accuracy observed from the simulation was 92.5% at 25 ms timing error for 16 devices per synapse.
We performed the training experiment with the synapses realized using eight on-chip PCM devices in differential configuration and the SNN generated more than 85% of the spikes within the 25 ms error tolerance (Fig. 3b).The training experimental results agree well with the observations from the PCM model based simulation.The training accuracy obtained from the corresponding 64-bit floating point (FP64) training simulation is also shown for reference.A raster plot of the spikes observed from the SNN trained in the experiment is shown in Fig. 3c as a function of time along with the desired spikes.The character images shown on top are created using the average spike rate for the duration of each character and it indicates that the network was successfully trained to generate the spikes to create the images.While the maximum accuracy obtained by the training the PCM devices is limited by the non-linearity, stochasticity, and granularity of its conductance change, we observed that accuracy of the SNN could be further enhanced by modifying the input encoding scheme.The ability of a neural network to classify its inputs depends on the correlation between the inputs.In Fig. 4 we show using the PCM model simulation that the accuracy gap between those from the experiment and floating point training simulation can be reduced by decreasing the correlation between the input spike streams.We added a random temporal jitter uniformly distributed in the interval [-25, 25] ms to each input spike which causes the cross-correlation between the input spike streams to decrease.The correlation coefficients between the binary spike streams were determined after smoothing them using a Gaussian kernel (e −t 2 /2σ 2 ) of σ = 5 ms.Even though the added jitter only reduces the correlation by a very small amount (Fig. 4b), the training performance improves substantially, suggesting that encoding schemes or network structures that inherently separate input features will improve training performance using low-precision devices such as PCM.

E. On-chip inference
The ability of a PCM based SNN to retain the trained state is evaluated by reading the conductance at logarithmic intervals of time and using it to calculate the network response.Both the spike-time accuracy (Fig. 5a) and the average spike rate (depicted as pixel intensities in Fig. 5c) drops due to conductance drift over time (Fig. 5b).The conductance decrease causes the net current flowing into the neurons to reduce which result in errors in spike times and a drop in the neuron spike rate.However, we show that this can be compensated via an array level scaling method described below.
The conductance drift in PCM is modeled using the empirical relation 44,45 : where G(t) is the conductance of the device at time t > t 0 , t p denotes the time when it received a programming pulse and t 0 represent the time instant at which its conductance was last read after programming.Thus, each programming pulse effectively re-initializes the conductance drift 27 .As a result, the devices in the array will drift by different amounts during training, based on the instant they received the last weight update.However, once sufficient time has elapsed after training, (i.e., when t becomes much larger than all the t p values of the devices in the array), the conductance drift can be compensated by an array level scaling.In our study, all the measured conductances were scaled by t 0.035 e where the t e is the time elapsed since training and 0.035 is the effective drift coefficient for the conductance range of the devices in the array.Fig. 5 shows the improvement in spike-time accuracy and spike rate obtained using this scaling method.The drop in accuracy after the compensation can be attributed to the conductance state dependency and variability of the drift coefficient.The inference performance of SNN using PCM synapses could be further improved by reducing the inherent conductance drift from the devices.The recently demonstrated projected-PCM cell architecture with an order of magnitude lower drift coefficient is a promising step in this direction 46,47 .

DISCUSSION
One of the key questions that we have evaluated in this work is the ability of stochastic analog memory devices to represent the synaptic strength in SNNs that have been trained to create spikes at precise time instances.As opposed to supervised learning in second generation ANNs whose network output is determined typically by normalization functions such as softmax, learning to generate multiple spikes at precise time instants is a harder problem.Compared to classification problems, the accuracy of which depends only the relative magnitude of the response from one out of several output neurons, the task here is to generate close to 1000 spikes at the desired time instances over a period of 1250 ms from 168 spiking neurons, which are only excited by 132 spike streams.Furthermore, the high correlation observed among several input spike-streams (due to the inherent correlations present in the frequency components of the input audio signal) also makes the learning problem challenging for networks with lowprecision weights.While the spike rate based pixel intensity plots clearly represents the desired images, we chose to evaluate our training performance using an accuracy metric defined in terms of spike time tolerance, since SNNs designed to process precise spike times rather than spike rates could be expected to have higher energy efficiency and smaller response time.
At the same time, the observed conductance characteristics of biological synapses is not all too different from those exhibited by our nanoscale phase change memory devices.PCM device conductance changes in a stochastic manner when programmed using partial-SET pulses, and the conductance saturates in approximately 16 − 20 pulses corresponding to a bit precision on the order of 4 − 5 bits.Synaptic transmission in biology is also observed to be stochastic and quantized, and previous studies have estimated that biological synapses have a precision of about 4.6 bits 48 .
However, a major difference between our experiments and biology is the dynamics of the spiking neurons and the learning algorithms used for weight updates.We have implemented the highly simplified leaky-integrate-and-fire model with an artificial refractory period to model the neuronal dynamics.Numerous studies have pointed out that neuronal integration and spiking in biology is a highly non-linear and error-tolerant process, with the most striking behavior revealed by the experiments of Mainen and Sejnowski showing extremely reliable spiking behavior of neocortical neurons when excited by noisy input currents 49 .Such non-linear behaviors may also play a key role in allowing biological networks to create spikes with more reliability and precision.
While several algorithms have been developed from mathematical formulations of cost-functions involving spike rates and spike times, the mechanisms employed by nature to achieve the same task are still not well-understood.Most of the neuroscience literature focuses on local learning rules such as hebbain plasticity, STDP, triplet-STDP, etc.It is not clear how these different local unsupervised learning rules come together to enable biological networks to encode and process information using precise spike times.Neverthless, the artificial algorithms being developed are achieving increasing amounts of success in showing software-equivalent performance in several common benchmark tasks in machine learning.
In summary, we analyzed the potential of the PCM devices to realize synapses in SNNs that can learn to generate spikes at precise time instances via large scale (approximately 180,000 PCMs) supervised training and inference experiments and simulations.We proposed several strategies to improve the performance of these PCM based learning networks to compensate for the device level non-idealities.For example, synapse update granularity improved via multi-PCM configurations can improve the training accuracy.Also, the performance drop during inference due to the conductance drift could be compensated via array level scaling based on a global factor which is a function of the time elapsed since training alone.We successfully demonstrate that in spite of its state-dependent conductance update and drift behavior, PCM synaptronic networks could be trained to generate spikes with a few milliseconds of precision in SNNs.In conclusion, PCM based computational memory presents a promising candidate to realize energy efficient bio-mimetic parallel architectures for processing time encoded SNNs in real time.

Audio to spike conversion
The silicon cochlea chip has 64 band-pass filters with frequency bands logarithmically distributed from 8 Hz to 20 kHz and generates spikes representing left and right channels.Further, due to the synchronous delta modulation scheme used to create the spikes, there were on-spikes and off-spikes.The silicon cochlea generated spikes with a time resolution of 1 µs.The spikes were further sub-sampled to a time resolution of 0.1 ms.The final input spike streams used for the training experiments have an average spike rate of 10 Hz.Combining all the filter responses with non-zero spikes for left and right channels and the on and off spikes, there are 132 input spike streams.

Neuron model
The SNN output neurons were modeled using leaky-integrate and fire (LIF) model.Its membrane potential V (t) is given by the differential equation where C m is the membrane capacitance, g L is the leak conductance, E L is the leak reversal potential, and I(t) is the net synaptic current flowing into the neuron.When V (t) exceed a threshold voltage V T , V (t) is reset to E L and a spike is assumed to be generated.Once a spike is generated, the neuron is prevented from creating another spike within a short time period called refractory period t re f .For the training experiment, we used C m = 300 pF, g L = 30 nS, E L = −70 mV, V T = 20 mV, t re f = 2 ms.For the NormAD training algorithm, the approximate impulse response of the LIF neuron is given as 1 C m e −t/τ L u(t) where τ L = 0.1 × C m /g L and u(t) is the Heaviside step function.During training, the neuron responses were simulated using 0.1 ms time resolution.

PCM platform
The experimental platform is built around a prototype chip of 3 million PCM cells.The PCM devices are based on doped-Ge 2 Sb 2 Te 5 integrated in 90 nm CMOS technology 50 .The fabricated PCM cell area is 50 F 2 (F is the feature size for the 90 nm technology node), and each memory device is connected to two parallel 240 nm wide n-type FETs.The chip has circuitry for cell addressing, ADC for readout, and circuits for voltage or current mode programming.
The PCM chip is interfaced with the Matlab workstation via FPGA boards and a high-performance analog-front-end (AFE) board.AFE implements digital to analog converters, electronics for power supplies, and voltage and current references.FPGA board implements digital logic for interfacing PCM and AFE board and perform data acquisition.A second FPGA board has an embedded processor and Ethernet unit for overall system control and data management.

Experiment
The SNN training problem was initially simulated using double-precision (FP64) synapses in the Matlab simulation environment.The weight range for the SNN was approximately in the range [-6000, 6000].To map the weights to the PCM conductance values in a multi-PCM configuration, the conductance range contribution from each device is assumed to be [0.1 µS, 8 µS].The conductance values are read from the hardware using a constant read voltage of 0.3 V, scaled to the network weights and are used for matrix-vector multiplications in the software simulator.When different number of PCM device are used per synapse, a scaling factor is determined such that the total conductance map to the same weight range.The weight updates determined from the training algorithm at the end of an epoch is programmed to the PCM devices using partial-SET pulses of a duration 50 ns and amplitudes in the range [ For inference, the PCM conductance values were read at logarithmic time intervals after 100 epochs of training and the effect of compensation schemes were evaluated in the software simulator.

FIG. 1 .
FIG.1.Spiking neural network implementation using computational memory array.a A single layer spiking neural network that translates an input set of spike trains to an output set of spike trains (top).The network connectivity matrix could be realized using a nonvolatile computational memory array (bottom).The voltage spike trains V i are applied along the word-lines and the weighed summations are read as currents I j from the bit-lines.b The characteristic state-dependent behavior of average conductance change observed in a phase-change memory (PCM) device.The device structure in the inset illustrates the amorphous region (amor-GST) formed inside the crystalline region (cryst-GST).c The synaptic conductance changes measured using changes in excitatory postsynaptic current (EPSC) as a function of its initial EPSC amplitudes, from the hippocampal neurons in a rat10 .The state-dependent nature of conductance change in response to positive (causal) spiking is analogous to that observed in the PCM devices.

FIG. 2 .
FIG. 2. SNN training problem.The audio signal is passed through a silicon cochlea chip to generate spike streams.These spike streams are sub-sampled and applied as input to train the single layer SNN.The desired spike response from the networks representing the images (14 × 12 pixels) corresponding to the characters in the audio is also shown.

FIG. 3 .
FIG. 3.Training experiment using PCM devices.a Simulated training accuracy as a function of the number of devices in a multi-PCM synapse (92.5% maximum accuracy).Accuracy is defined as the fraction of the spike events in the desired pattern corresponding to which a spike was generated from respective output neurons within a certain time interval.The lower bound of the shaded lines correspond to 5 ms interval, the middle line to 10 ms and the upper bound to 25 ms.b Accuracy as a function of training epochs from the experiment using on-chip PCM devices.Each synapse was realized using 8 PCM devices in differential configuration.The corresponding training simulation using the PCM model shows excellent agreement with the experimental result.The experiment, PCM model, and the reference floating point (FP64) training achieve maximum accuracies of 85.7%, 87%, and 98.9% respectively for the 25 ms error tolerance.c The raster plot of the desired and observed spike trains from the trained network.A visualization of the character images whose pixel intensities are generated from the observed spike rates is also shown above the raster plot.

FIG. 4 .
FIG. 4. Role of input correlations in network performance.a Input spike streams with spike times jittered by random amounts uniformly distributed in [-25, 25] ms.b The cross-correlation between the jittered spike streams are shifted towards zero compared to the experimental input c The simulated training accuracy is improved when trained with input spike streams of reduced correlation.

FIG. 5 .
FIG.5.On-chip inference and drift compensation.a Inference using trained PCM array.Due to conductance drift, the accuracy drops over time (black line).The effect of drift can be compensated by a time-aware scaling method (red line).Percentage accuracy drop over 4×105 s was reduced from 70% to 13.6% at 25 ms error tolerance.b The drifted conductance distribution at the end of 10 5 s is compared with the trained conductance distribution.The effect of scaling on the drifted conductance is also shown.c The images generated by the SNN at the end of training for the audio input (top).The images generated after 10 5 s (middle).The images generated with drift compensation (bottom).The brightness of each pixel represents the spike rate for the duration of each character.
40 µA, 130 µA].The device conductance values are read after each epoch and is used to update the SNN synapse values.Since each conductance values are read and programmed in series, each training epoch was emulated in an average of 6.3 s.