Table 2 Scaling of the design for 45 nm CMOS technology and comparison to 180 nm.

From: Memristive GAN in Analog

ComponentPower (mW)PowerArea (μm2)Area changeDelay (ps)Delay changeTC var. range (offset)TC var. changeL var. (offset)L var. change
Separate circuit components
ReLU0.053↓53%1.479↓94%100↓70%±60 mV↑60%±0.2 V↑60%
LeakyReLU2.050↓5%2.037↓94%80↓81%±60 mV↑65%±0.2 V↑60%
Tanh0.017↓85%0.062↓76%64↑44%±80 mV↑50%±0.3 V↑67%
OpampL = 45 nm2.290↓72%2.724↓94%160↓74%±0.1 V↑50%±0.25 V↑25%
L = 90 nm0.798↓90%5.448↓88%650↑5%±12 mV↓88%±50 mV↓75%
WSS circuitL = 45 nm2.719↓93%8.744↓92%650↑61%±10 mV↑90%large variation*3
L = 90 nm1.320↓97%11.468↓90%4000↑94%±0.1 V*2±0.3 V*4
CS circuit11.00*1↓2%0.675↓94%120↓31%no variation±1mA*5↑50%
ComponentPower (mW)Area (μm2)Delay (ns)Output errors*6
Filters and crossbars (comparison of 180 nm and 45 nm CMOS circuits)
Convolutional filter with LeakyReLU180 nm40.16177.721.28Diff.amplifier: 0.9 mVReLU: 0 mV
45 nm1.6310.841.88Diff.amplifier: 0.24 mVReLU: 0.2 mV
Convolutional filter with Tanh180 nm40.08142.171.15Diff.amplifier: 0.9 mVTanh*7: 0.3 mV
45 nm1.388.861.80Diff.amplifier: 0.17 mVTanh*7: 0.2 mV
Dense layer crossbar with LeakyReLU180 nm441.914541.45WSS(i): 1.04 mVWSS(n): 0.76 mVCS: ~0 mVIVC: 0.3 mVL.ReLU: ~0 mV
45 nm15.53131.96.25WSS(i): 2.15 mVWSS(n): 0.63 mVCS: ~0 mVIVC: 0.8 mVL.ReLU: ~0 mV
  1. *1Depends on the current; *2for input voltages >0.8 V; *3distortion of the output; *4can cause distortion of the output in rare cases; *5only for the input >8 mA; *6example for particular case; *7for small input (error in the slope; Abbreviations: L.ReLU-LeakyReLU, WSS(i/n)- inverted/non-inverted output of WSS).