High Performance All Nonmetal SiNx Resistive Random Access Memory with Strong Process Dependence

All-nonmetal resistive random access memory (RRAM) with a N+–Si/SiNx/P+–Si structure was investigated in this study. The device performance of SiNx developed using physical vapor deposition (PVD) was significantly better than that of a device fabricated using plasma-enhanced chemical vapor deposition (PECVD). The SiNx RRAM device developed using PVD has a large resistance window that is larger than 104 and exhibits good endurance to 105 cycles under switching pulses of 1 μs and a retention time of 104 s at 85 °C. Moreover, the SiNx RRAM device developed using PVD had tighter device-to-device distribution of set and reset voltages than those developed using PECVD. Such tight distribution is crucial to realise a large-size cross-point array and integrate with complementary metal-oxide-semiconductor technology to realise electronic neurons. The high performance of the SiNx RRAM device developed using PVD is attributed to the abundant defects in the PVD dielectric that was supported by the analysed conduction mechanisms obtained from the measured current–voltage characteristics.

distributions of PVD-SiN x and PECVD-SiN x devices, which are ranged from 6.8 to 8.2 V and from 11.0 to 13.7 V, respectively.
To further understand the carrier conduction mechanism, we analysed the measured data by using various transport mechanisms. Because there is no metal inside the dielectric to form the metallic filament, the conduction mechanism of nonmetal RRAM device is attributed to defect-related hopping conduction 10,12,13 . Figures 2 and 3 display the analysed conduction mechanisms for PVD-SiN x and PECVD-SiN x RRAM devices, respectively. The very low HRS current in the PVD-SiN x RRAM devices, as presented in Fig. 2, is attributed to the space-charge limited conduction (SCLC) mechanism [14][15][16]28 . The SCLC regions are divided into three regions by using the transition voltage V tr and trap-filled limited voltage V TFL . For the low-bias voltage region that is less than V tr , the current is proportional to voltage and follows Ohm's law, with an extremely high resistance of approximately 10 GΩ. The current density-voltage (J-V) relationship obtained when the applied voltage is larger than V tr but lower than V TFL (region 2) can be expressed as follows 17,29 : where J, μ, ε, d, and θ represent the current density, electron mobility, static dielectric constant, dielectric layer thickness, and ratio of the free current density to the trapped and free current densities, respectively. In this region, shallow traps are gradually filled by increasing the electric field, and the injected free carrier current density J free significantly contributes to the total current density. All the traps at voltages larger than V TFL are filled by injected carriers. A massive number of free carriers contribute to current conduction under a high electric field, thus leading to a steep current-voltage (I-V) slope (region 3) For the PVD device, the currents of HRS I-V curves increase with increasing temperature 18 . Conversely, the LRS, which exhibited ohmic-like behavior, can be analysed with a slope of 1.3 9,13 .
For the HRS current of the PECVD-SiN x devices presented in Fig. 3(a), the current conduction resembles Poole-Frenkel (P-F) emission 19,20,[29][30][31][32] : and T are the current density, electron drift mobility, density state in the conduction band, energy level of trap, electric field, dynamic permittivity, vacuum permittivity, Boltzmann's constant, and absolute temperature, respectively. A trap energy qφ T of 1.1 eV was determined according to the Arrhenius plots presented in Fig. 3(a) at a temperature range from 298 to 398 K. An ε i value of 4.3 was obtained from the slope of P-F plots and is lower than the static permittivity (ε = 7) 33 . P-F emission occurs due to electrons hopping between nearby traps 34 which leads to a high HRS current, as shown in Fig. 1(b). Figure 3(b) displays the LRS I-V characteristics of the PECVD-SiN x device that adheres to the SCLC under the most-negative voltage bias region. Figure 4 illustrates the potential switching behaviours of the SiN x RRAM device. The PVD-SiN x dielectric has abundant defects in the initial condition because of its room temperature deposition with a low annealing temperature of 200 °C. The current conducting path can be formed and switched to LRS with a relatively low I cc value and voltage. By contrast, the PECVD-SiN x dielectric was deposited at a relatively high temperature of 300 °C, with fewer defects, so the conducting path could not be formed under low I cc and voltage values. Therefore, a high forming voltage of 12 V and a high I cc of 1 mA were required. Under such a high electric field, a large number of Si-N bonds were broken and excessive defects were created. The excessive defects in the PECVD-SiN x layer www.nature.com/scientificreports www.nature.com/scientificreports/ may create multiple conduction paths and lead to a high HRS current, as shown in Fig. 1(b). To switch from LRS back to HRS, a negative V reset was applied to rupture the conducting path. Although the conducting paths were ruptured, the electrons in the PECVD-SiN x layer had a high possibility to conduct current in parallel ways via  The deposited SiN x layers were further analysed using X-ray photoelectron spectroscopy (XPS). Figure 5(a,b) depict the XPS data for PVD-SiN x and PECVD-SiN x layers, respectively. The related Si 2p spectra obtained from the XPS data are displayed in Fig. 5(c,d) for the PVD-SiN x and PECVD-SiN x layers, respectively. The N-Si composition of the as-fabricated PVD-SiN x and PECVD-SiN x layers were 0.91 and 1.08, respectively, which indicates a high number of defects inside the PVD-SiN x layer. The nitride vacancies 21,35 and Si dangling bonds 22,23 can play crucial roles to form the conducting path. The slightly higher oxygen content in the PVD-SiN x layer than in the PECVD-SiN x layer cannot explain the significantly better device performance because the bond enthalpy of SO is higher than that of SN. That is, it is more difficult to break the SO bond to form the defects. Therefore, the XPS results support the proposed model depicted in Fig. 4 and adequately explain the measured I-V characteristics in Fig. 1 and the analysed current conduction mechanisms in Figs. 2 and 3. Such defect-assisted conduction is also the major mechanism for similar GeO x RRAM devices 10 . The conducting path can be constructed or broken by the different polarities of the applied voltage.
Device endurance and data retention are the crucial characteristics of a nonvolatile memory. Figure 6 shows the retention data of PVD-SiN x and PECVD-SiN x RRAM devices under an 85 °C test condition. The PECVD-SiN x device exhibits a much smaller resistance window and a rapid degradation from an initial value of 56 to 11 after 10 4 s retention at 85 °C. The poor retention can be ascribed to the high forming voltage with large kinetic energy; then the electrons at 85 °C can partially annihilate or create a leakage path with multiple defects, as shown in Fig. 4. By contrast, the resistance window of an all-nonmetal PVD-SiN x RRAM device slightly decreases from 1.8 × 10 3 to 1.3 × 10 3 after a retention time of 10 4 s at 85 °C. The RRAM device endurance data are shown in Fig. 7, where the V set and V reset pulses of +5 V and −5 V were applied to devices with a 1-μs pulse width. The resistance window of the PECVD-SiN x device degraded quickly, and the device failed after 10 3 endurance cycles. Conversely, a large resistance window of two orders of magnitude was obtained for the PVD-SiN x RRAM device, even after 10 5 pulse cycles. The excellent endurance of the PVD-SiN x device is related to the high number of defects that can be set and reset easily, with less destruction to the dielectric material. Figure 8(a,b) display the device-to-device and cycle-to-cycle distributions of V set and V reset respectively, which are critical for the RRAM cross-point array [24][25][26] . The coefficient of variation (CV) was used to study the distribution and is defined as follows: www.nature.com/scientificreports www.nature.com/scientificreports/ where σ is the standard deviation, and μ is the mean value. The lower CV value represents a tighter distribution and is crucial for a larger array size 26 . The device-to-device distributions were extracted from 25 different devices. The CVs of V set and V reset of the PVD-SiN x RRAM were 10.7% and 12.1%, respectively, which are remarkably tighter than the 18.3% and 23.2% of PECVD-SiN x devices, respectively. The cycle-to-cycle variations of the first 100 consecutive DC switching cycles, depicted in Fig. 8(b), also show the crucially tighter operation voltage distributions of PVD-SiN x RRAM devices than those of PECVD-SiN x ones. During the forming step, the dielectric soft breakdown must occur by breaking part of the SiN bonds. Based on the preceding discussion, the PECVD-SiN x RRAM device requires a higher I cc value and voltage during fabrication to create a conducting path that has an excessive number of defects and an uncontrollable reset current. These results further lead to poor V set and V reset distribution and fewer endurance cycles. One issue of nonmetal RRAM device is the relatively larger operation voltage than that of metal-oxide RRAM device, even though the operation voltage is still much less than that of a flash memory 36 . One possibility to lower the operation voltage is to use the weak bond-enthalpy GeO x dielectric 9 , in which the defect-related conduction path can be formed by breaking the dielectric at low energy.

conclusion
High-performance all-nonmetal N + -Si/SiN x /P + -Si RRAM devices were achieved. The device performance was highly dependent on the deposition process. In this process, the current conduction in the RRAM device was highly related to the defects inside the SiN x layer. The PVD-SiN x RRAM devices exhibited favourable memory characteristics: a large memory window, high pulsed endurance, a long data retention time at 85 °C, and tight   www.nature.com/scientificreports www.nature.com/scientificreports/ device-to-device V set and V reset distributions. The PVD-SiN x RRAM device has high potential to realise a large-size cross-point memory array and to be embedded in CMOS technology to realise electronic neurons.

Methods
A P + silicon wafer was used as a bottom gate. After conducting the RCA clean for the wafer and dipping the wafer into dilute HF to remove the native oxide, a 25-nm-thick SiN x layer was formed by either PVD using electron-beam evaporation or PECVD. Additional furnace annealing was applied to the PVD-SiN x layer at 200 °C in a N 2 ambient for 30 min. For the PECVD-SiN x layer, a NH 3 of 6 sccm, 8% SiH 4 in Ar of 125 sccm, and N 2 of 200 sccm were used at a temperature of 300 °C. Finally, the N + -Si top electrode was fabricated as the top electrode with a diameter of 120 μm 11 . The electrical characteristics were measured using the HP4155B analyser. The pulse stress was generated using a pulse generator (81110, Agilent). Material analysis was performed through XPS analysis by using Thermo Scientific K-Alpha with an X-ray spot size of 400 μm.