Table 5 SLIM bitcell count, Normalized Energy/Operation and Normalized latency count for different operations using SLIM NAND/NOR logic gate.

From: SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices

Logic Operation Type1T-1R (NAND)2T-1R (NOR)
#SLIM bitcellsNorm. Energy/OpNorm. Latency#SLIM bitcellsNorm. Energy/OpNorm. Latency
OR32
AND23
NOR41
NAND14
XOR45
XNOR54
-bit Half Adder55
-bit Full Adder99
  1. (All values normalized w.r.t. SLIM 1T-1R NAND and provide worst-case estimates i.e. maximum device switching).