Table 1 Salient Features of different LIM techniques proposed in literature.

From: SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices

RefBuilding BlockLogicSalient Features
10BRSa and CRSb cellsNon-Statefulc V-R logic (sequential logic)14 out of 16 Boolean function realized in maximum 3 cycles, retains logic output, destructive read operation
111 BRSNon-Stateful V-R logic (sequential logic)all 16 Boolean function realized in maximum 3 cycles, retains logic output, needs rectifying behavior
121 CRSNon-Stateful V-R logic (sequential logic)all 16 Boolean function realized in maximum 3 cycles, retains logic output, needs rectifying behavior
132 BRS (connected anti-serially)Non-Stateful V-R logic (sequential logic)all 16 Boolean function realized in max. 3 cycles, retains logic output
143 BRSStatefuld R-R Logic5 basic Boolean functions can be realized in 2 cycles, retains input variables and logic output
151T-1RNon-Stateful V-R logic (sequential logic)all 16 Boolean function realized in 2 cycles (+1 read cycle), retains input variables and logic output
163 BRS + passive resistorStateful R-R LogicNAND, AND and other logics can be realized using different number of BRS devices or cascading, retains both input variables and logic output
173 BRS + passive resistorStateful R-R LogicBoolean function except XOR and XNOR in 1 cycle, retains input variables and output
181R (4 resistance states) + passive resistorStateful R-R Logicall 16 Boolean operations are realized, retains logic output
This Work2T-1R or 1T-1R (R:4 resistance states)Non-Stateful V-R logic5 basic Boolean functions in 1 cycle, retains initial Memory state and logic output (not storing input variables)
  1. aBipolar restive switches, bComplementary resistive switches, cinput (voltage signal) and output (resistance) are in different forms, dinput and output are in the same form i.e. either both are voltage signals or recorded in terms of device resistance.