Figure 5 | Scientific Reports

Figure 5

From: SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices

Figure 5

Four possible input operand combinations: (a) a = b = ‘0’; (b) a = ‘0’, b = ‘1’; (c) a = ‘1’, b = ‘0’; (d) a = b = ‘1’; corresponding to NAND truth table and proposed signal mapping for each case for the 1T-1R SLIM bitcell. [VTB = VTE − VBE; operand a is mapped to VG = 10 V (7 ms long); operand b is mapped to V2 = P3 = 5.5 V (7 ms long)]. Experimental results for NAND logic implemented using 1T-1R SLIM bitcell with device’s initial state: ‘11’ (eh), and ‘01’ (il). Among the four operand combinations, OxRAM device switches to Logic HRS state (‘10’ or ‘00’) only for a = b = ‘1’. Blue: transient current through OxRAM device.

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