Introduction

Thin-film transistors (TFTs) has been widely applied for high-performance electronics applications such as Active Matrix Organic Light Emitting Diodes (AM-OLED). High-performance TFTs with a high mobility, a low threshold voltage, and a low swing slope can reduce the power consumption and enhance the quality of flat-panel display1,2,3,4,5. Therefore, various studies has be carried out to improve the electrical performance of TFTs, such as adopting different device structures6, using different channel materials, and optimizing the fabrication processes7.

TFTs fabricated by solution processing and inkjet printing have the advantage of low cost, while suffering from a low mobility and a high annealing temperature8,9. TFTs based on 2-dimentional (2D) materials such as graphene and Molybdenum disulfide (MoS2) have been widely investigated recently due to their excellent electrical properties10,11. However, 2D materials-based TFTs still have some challenges in large-scale fabrication of high quality devices, not compatible with modern Silicon-based microelectronic technologies. Zinc-oxide (ZnO) based TFTs have attracted considerable attention for their superior electrical and optical properties since last decade2,3,12,13,14. Among ZnO-based multicomponent oxide TFTs, In-Ga-Zn-O, Al-Zn-O, In-Zn-O, Zn-In-Sn-O TFTs had been proved to be attractive alternatives to conventional silicon-based TFTs in AMOLED due to their high mobility, low threshold voltage, fully transparency, and large-area applications15,16,17,18,19,20,21. While most of these work required a high processing or annealing temperature (above 300 °C). These thermal processes increase the manufacturing cost and limits their application in flexible display where a low processing temperature (<100 °C) is desirable15,22,23. Thus, alternative ZnO-based TFTs fabricated at a low temperature still need to be investigated. Sn-doped ZnO (TZO) has the advantages of high mobility and low temperature processing compatibility24,25. While the research of TZO TFTs received less attention and the device performance presented is undesirable. High-performance TZO TFTs fabricated at a low temperature are still of interest. Therefore, the goal of our research is to realize high-performance TZO TFTs at a low temperature.

The idea of adopting multi-stacked active-layer structures to improve the performance of TFTs has been previously investigated26,27,28,29,30. TFTs with LaTiO3/SrTiO3 heterostructure and ZnO-based ZnO/Zn1−xMgxO heterostructure has been proved to exhibit a higher mobility than TFTs with conventional thin films and bulk materials29,31,32. Multi-stacked channel structures were also adopted in solution processed TFTs to improve the mobility of devices26,27. However, a systematic work to probe the performance of TZO TFTs with multi-stacked active-layer structure at a low processing temperature is still lacking. Previously, we reported improving the performance of TZO TFTs with various strategies such as adding oxygen during the deposition of TZO layers33,34, adopting DAL ITO/TZO TFTs35,36, and adjusting the thickness of the ITO/TZO active layer37. We demonstrated that TZO TFTs are promising switching devices for flat-panel applications. The DAL TFTs can effectively improve the mobility and reduce the threshold voltage. However, the DAL TFTs have a high off-state current due to the high carrier density in the ITO layer, leading to a higher power consumption. Therefore, we aim to optimize the channel structure of TFTs to reduce the off-state current and improve the on-off current ratio.

In this paper, we compared the performance of TFTs with different channel structures and demonstrated that high-performance TZO TFTs can be realized at a low temperature (80 °C) by adopting TAL stack for TFTs. Compared to TFTs with SAL or DAL channel configuration, the proposed TAL TZO/ITO/TZO TFTs exhibit a higher mobility and a lower threshold voltage. The quality of the TZO film and ITO films were characterized by AFM, SEM, and XRD. The stability and uniformity of our fabrication process is confirmed by the consistent performance of TAL TFTs with different channel lengths. A physical mechanism for the electrical improvement is also deduced. The proposed TAL TFTs are promising in various applications due to the superior performance, low-processing temperature, and low cost.

Results

Device structure and fabrication process

A schematic of the device structure is shown in Fig. 1a. A bottom-gate TFT was fabricated on a glass substrate by standard photolithography and lift-off techniques, without any intentional substrate-heating process. All procedures were carried out below 80 °C. A top-view optical image of a representative device is shown in Fig. 1b. The device was fabricated using a 3 photo-masks process, as shown in Fig. 2. The detailed fabrication procedures are described in methods.

Figure 1
figure 1

(a) Schematic illustration of the device structure. An inverted staggered structure was adopted in this research. The channel layer and the dielectric layer are patterned using the same mask. (b) An optical photo (top view) of a representative device in this paper.

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Figure 2
figure 2

Fabrication process of the TFTs with three different channel configurations: channel type 1 (SAL), channel type 2 (DAL), and channel type 3 (TAL). The devices were fabricated from step 1 to step 4, successively.

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Electrical measurements

Figure 3a–c shows schematics of three different channel configurations: SAL, DAL, and TAL. Figure 3d shows the representative transfer curves of TFTs with three different channel configurations: TZO/ITO/TZO (TAL), ITO/TZO (DAL), and TZO (SAL). All the devices have the same channel dimension with a channel aspect ratio of 100 μm/20 μm. The drain to source voltage was biased at 5 V. Back-gate voltage was biased from −4V to 10 V. The transport measurements were carried out under ambient condition at room temperature. Figure 3d shows that the TAL TFTs have the best performance with a high on-off state current ratio (Ion/Ioff) of ~2 × 108 and a low Vth of ~0.6 V. Moreover, TAL TFTs has a high μFET of 128.6 cm2/Vs and a low Ioff of 3.3 pA. The Swing Slope (SS) was calculated by the Eq. (1), while Vth and μFET were extracted by the Eq. (2). Cox of 2.6 × 108 F/cm2 was extracted from C-V curve of 100 K Hz38.

$$SS=\frac{\partial {V}_{GS}}{\partial (log{I}_{DS})}{/}_{{V}_{DS}=con}$$
(1)
$${I}_{DS}=\frac{W}{2L}{\mu }_{FET}{C}_{ox}({V}_{G}-{V}_{th}){V}_{DS}$$
(2)
Figure 3
figure 3

Schematic of (a) TZO single-active layer, (b) ITO/TZO dual-active layers, (c) TZO/ITO/TZO triple-active layers. (d) Representative transfer curves of TFTs with the three different channel configurations.

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Figure 4 compares the electrical properties of TFTs with three different channel configurations. Figure 4a compares the μFET of the devices. We can see that comparing to SAL TZO TFTs, the TFTs with TAL and DAL channel configurations have a much higher μFET (roughly 5 times higher). This high mobility is due to the good conductivity of the ITO layer in the channel39. Figure 4b compares the Ion/Ioff and Vth and shows that the TAL TFTs have the lowest Vth and the highest Ion/Ioff. The DAL TFTs and SAL TFTs has similar Ion/Ioff. After adding the ITO layer, both the Ion and Ioff of the DAL TFTs are increased. Compared to SAL TFTs, DAL TFTs has the advantages of high μFET and low Vth while also suffering from a high Ioff, which may leads to higher power consumption in applications. The TAL TFTs combine the advantages of SAL TFTs (low Ioff) and DAL TFTs (high μFET and low Vth). Figure 4c shows the variation of SS due to back gate voltage in TFTs with TAL, DAL, and SAL, respectively. All the TFTs have similar values of SS (~0.3 V/dec.). Figure 4d shows the channel resistivity of the SAL stack, DAL stack, and TAL stack, which was measured using 4-probe station. The SAL stack and TAL stack have roughly the same channel resistivity, ~20 times larger than that in DAL stack. This confirms the lower Ioff in TAL and SAL TFTs while the higher Ion in DAL TFTs, shown in Fig. 3d. Extracted parameters were summarized in Table 1.

Figure 4
figure 4

Comparison of the electrical properties of TFTs with different channel structures. (a) field effect mobility, (b) on-off state current ratio and threshold voltage, (c) subthreshold slope, and (d) channel resistivity.

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Table 1 Extracted parameters of the TFTs studied in this paper.
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These electrical results are originated from the different roles of each film in the channel. As the n-channel TZO TFTs operated on enhancement mode, most of the induced carriers go either into the deep localized states in the TZO layer or into the interface states when the gate bias voltage VGS < 0 V. Only a very small fraction of electrons that are close to the front of TZO/SiO2 interface (interface near to the gate electrode) participate in channel conduction, resulting in a low Ioff. While as the VGS increases, the channel conductivity increases rapidly due to charges accumulating in the TZO layer, yielding a suitable a high Ion. The TZO channel controls the charge conductance to get a high Ion/Ioff and a suitable Vth. While for DAL ITO/TZO TFTs, the high mobility electron gas formed in the high density interface of the ITO/TZO heterostructure, leading to a higher mobility and Ion. The TZO layer provides a suitable Vth due to its controlling ability in the charge conductance. Compared to TZO conducting layer, the thin ITO layer of the DAL ITO/TZO channel provides a higher carrier concentration, therefore maximizing the charge accumulation and yielding a high μFET, while suffering a high off-state current40.

For TAL TFTs with TZO/ITO/TZO channel strucutre, there are three different interfaces that affects the electrical characteristics of the device: two ITO/TZO interfaces (above and below the ITO layer) in the channel stack, and the TZO/SiO2 interface. The high-density TZO/ITO interface and the high charge density ITO layer form electron gas and account for the high mobility and high saturation current. The TZO/SiO2 interface may not have high trap density as the swing slope in this device is low. During the turn on and off operation, less electrons are trapped in TZO/SiO2 interface. The TZO layer has low charge density and maintain low Ioff, thus the device has good controllability on the channel conductance.

From the resistance point of view, the ITO layer reduces the channel resistance of ITO/TZO TFTs while encapsulating the ITO layer between two TZO layers can increases the channel resistance. The schematic illustration of the three different channel configurations is shown in Fig. 5. Compared to the SAL TZO TFTs, the high carrier density in the ITO layer, leads to smaller channel layer resistance Rch22 and Rch32 (shown in Fig. 5b,c)41, resulting in a smaller overall resistance of ITO/TZO TFTs (Roverall2) despite small contact resistance Rcon and Rcon2. Using the Eq. (3):

$${I}_{off}=\frac{{V}_{DS}}{{R}_{overall}}$$
(3)
Figure 5
figure 5

Schematic cross-sectional view of the overall resistance in (a) SAL TZO TFTs, (b) DAL ITO/TZO TFTs and (c) TAL TZO/ITO/TZO TFTs. RSD is the resistance in the source and drain electrode, RCON, RCON2, RCON3 are the interface resistances between interface and RCH11, RCH21, RCH22, RCH31, RCH32, RCH33 are the resistances in the active layers.

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While for the TAL, thinner TZO layer has lower carrier density, yielding larger channel resistances Rch31 and Rch33, the series resistance Rcon3 also adds to Roverall3 (shown in Fig. 5(c))37,42. Thus, Roverall3 is larger than the Roverall2. This can be confirmed by the resistivity shown in Fig. 4d. Therefore, the TAL TFTs have lower Ioff than the DAL TFTs.

Output characteristics and device stability

Figure 6a shows the output characteristics of the TAL TFTs. The TAL TFTs work on enhancement mode and the back-gate voltage was set from 0 V to 5 V with a step of 1 V. The drain and source voltage scans from 0 V to 12 V. The drain current is raised rapidly within 1 V between drain and source and a clear saturation region can be observed. This demonstrates the good switch controlling ability (switch from off-state to on-state rapidly) of the device. Figure 6a shows that the saturation current exceeds 300 µA at a low back-gate voltage of 5 V. This indicates good current driving ability in the TAL TFTs. However, nonlinear correlation between the VDS and the IDS was also observed for VDS < 1 V. This may be due to the parasitic resistance induced by trap states near source and drain regions, leading to the current crowding phenomenon. Part of the drain voltage may drop on the parasitic resistance43. Due to the limitation of our setup, all the electrical characteristic measurements were performed under ambient condition. Oxygen may be adsorbed on the top of the channel and form a depletion layer. This may also lead to current crowding phenomenon. More work can be done to improve the quality of the contact interface but that’s out of the scope of this paper. Moreover, later work can optimize the device structure by adding an insulating layer on top of the channel to prevent this problem.

Figure 6
figure 6

(a) Output characteristics of the TAL TFTs. (b) Representative transfer characteristics of TAL TFTs with channel length of 20 µm, 80 µm, and 100 µm.

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To investigate the stability and the uniformity of our fabrication process. TAL TFTs with different channel lengths are also fabricated and measured. Figure 6b shows the representative transfer characteristics of TAL TFTs with three different channel length 20 µm, 80 µm, and 100 µm. The related parameters were extracted and shown in Table 1. All the devices have comparable mobility higher than 100 cm2/Vs and high on-off state current ratio higher than 108. This indicates our fabrication process is stable and uniform.

Material surface morphology and transparency

Figure 7a,b show the AFM surface morphology of the ITO and TZO film, respectively. The RMS is 0.8 nm and 1.9 nm, respectively. The smooth surface of the ITO film indicates better conductance of the film while the TZO film has a granular surface morphology with a larger surface roughness. The X-ray diffraction in Fig. 7c has one prominent peak at 34.3°, indicating Sn atoms successfully replace Zn sites in the lattice and form C-axis-aligned crystalline (CAAC)44,45,46. The average grain size of the TZO film is estimated to be 17.1 nm using the Scherer formula, this can also be confirmed by the SEM image shown in Fig. 7d.

Figure 7
figure 7

Surface characterization off the ITO and TZO films. (a) AFM image of the ITO film. (b) AFM image of the TZO film. (c) XRD diffraction pattern of the TZO film. (d) SEM micrograph of the TZO film. The scale bar for AFM images and SEM images is 200 µm.

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Discussion

For SAL TZO TFTs, oxygen was intentionally added during the RF sputtering process of the TZO film to reduce oxygen vacancy in the material, leading to reduction the hole density in the channel, which can reduce the off-state current and improve the swing slope of the device34. This can explain the low off-state current in SAL TZO TFTs. For the DAL ITO/TZO TFTs, ITO layer with a high carrier density was introduced to form channel layer. The high carrier density improves the mobility and the on-state current. Though the DAL ITO/TZO TFTs have superior performance including a high mobility, a low Vth, and a low SS, the high off-state current will lead to a high power consumption in real applications. The TAL channel configuration proposed in this paper has lower off-state current and still maintain a high mobility, can effectively solve this problem. Note that the thickness of the channel stack can also affect the performance of the devices. We have previously reported TZO TFTs and ITO/TZO TFTs with various TZO film thickness and ITO film thickness36,37. The thickness of the channel layers of the SAL TFTs and DAL TFTs in this research has been optimized. Thus, we can eliminate the effect of channel thickness when comparing the performance of devices with three different channel configurations. A more systematic work on optimizing the thickness of TAL stacks can be done to further improve the performance of the TAL TFTs. But this would not affect our comparison of the three channel configurations and demonstration of the superior performance of the TAL TFTs.

Conclusions

In this paper, we compared the electrical properties of TFTs with three different channel configurations including SAL, DAL, and TAL. Compared to SAL TFTs, DAL TFTs has a higher mobility and a lower SS due to the high carrier density from the ITO layer. While DAL TFTs suffer from a high off-state current, which leads to a higher power consumption in real application. The TAL TFTs were proposed to solve this problem. The proposed TAL TFTs combine the advantages of both SAL TFTs and DAL TFTs and exhibit superior electrical performance such as a high on-off state current ratio of 2 × 108, a low Vth of 0.63 V, a high μFET of 128.6 cm2/Vs, and a low off-state current of 3.3 pA. Owing to its advantages of low-processing temperature and superior electrical performance, TFTs with the proposed TAL channel configuration are highly promising for oxide semiconductor TFTs manufacturing and have application in flexible displays where the use of heat-sensitive polymeric substrates is desirable. Thus, this investigation is very crucial for commercial applications.

Methods

Device fabrication

The fabrication procedures are described as follows: (1) A gate electrode was patterned and a 150-nm thick ITO film was deposited by radio frequency (RF) magnetron sputtering at room temperature (RT) in Ar (pressure: 1.2 Pa and power: 70 W). (2) A 150-nm thick SiO2 was grown using plasma-enhanced chemical vapor deposition (PECVD) with a mixture of SiH4 and N20 (ratio 65:130) at 80 °C. (3) Channel layers were deposited by RF sputtering at room temperature in Ar/O2 mixture (flow rate ratio 100/8) with a power of 70 W. The target adopted for sputtering was a ceramic target with a mass ratio of ZnO: SnO2 = 97: 3. In this paper, TFTs with three different channel configurations were fabricated. (a) Single-active-layer TFTs (SAL TFTs) with single TZO layer (channel type 1 in Fig. 2), a 45-nm thick TZO was growth by RF sputtering. (b) Dual-active-layer TFTs (DAL TFTs) with ITO/TZO stack (channel type 2 in Fig. 2), a 5-nm thick ITO was first deposited and followed by depositing a 45-nm thick TZO. (c) Triple-active-layer TFTs (TAL TFTs) with TZO/ITO/TZO stack (channel type 3 in Fig. 2), 22-nm thick TZO, 5-nm ITO, and 22-nm TZO were deposited sequentially by RF sputtering. (4) After patterning the source and drain electrodes, a 150-nm thick ITO film was RF sputtered and lifted to form the source and drain electrodes.

Device measurement and materials characterizations

The surface morphology of the TZO films and ITOs films were evaluated by atomic force microscopy (AFM) and scanning electron microscope (SEM). The structure of the TZO film was analyzed by X-ray powder diffraction (XRD). The channel resistivity was obtained from four-probe station. The transport properties of the TFTs were characterized by a semiconductor parameter analyzer (Agilent 4156C). The resistivity of the stacks was measured using the 4-probe station.