Two-Dimensional-Like Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Low Operation Voltage

In this work, we have successfully demonstrated the junctionless (JL) transistors with two-dimensional-like (2D-like) nano-sheet (NS) material, amorphous indium tungsten oxide (a-IWO), as an active channel layer. The influences of the different gate insulator (GI) materials and the scalings of GI thickness, a-IWO channel thickness, and channel lengths on the a-IWO NS JL transistors (a-IWO NS-JLTs) have been studied for the purposes of low operation voltage (gate voltage ≤2V) and high performance. The 2D-like a-IWO NS-JLTs exhibit low operation voltage, low source/drain (S/D) contact resistance (RC) and other key electrical characteristics, such as high field-effect mobility (μFE), near ideal subthreshold swing (S.S.), and large ON/OFF currents ratio (ION/IOFF). The remarkable device characteristics also make the proposed 2D-like a-IWO NS-JLTs promising for system-on-panel (SoP) and vertically stacked (VS) hybrid CMOS applications.

amorphous indium tungsten oxide (a-IWO) semiconducting material with high mobility and stability, which is free from both Ga and Zn, was studied for an alternative choice to a-IGZO TFTs [13][14][15] . We have successfully fabricated and demonstrated the low thermal budget 2D-like a-IWO NS JL transistors (a-IWO NS-JLTs) in bottom metal gate (BMG) configurations with high μ FE ~25.3 cm 2 /V-s, near ideal S.S. ~63 mV/dec., and improved hysteresis characteristics for the first time 16 . The thickness of conductive a-IWO NS channel can be well controlled by radio-frequency (RF) magnetron sputtering at room temperature. The a-IWO NS-JLTs with metal S/D electrodes exhibit ultra-low leakage currents owing to the wider band gap of a-IWO compared to Schottky-barrier Si devices with high leakage currents 17 . Furthermore, the R SD also can be significantly reduced by using metal S/D electrodes.
In this work, we will study the influences of the different gate insulator (GI) materials and the scalings of GI thickness, a-IWO channel thickness, and channel lengths on the electrical characteristics and performances of a-IWO NS-JLTs. In addition, a low power and high performance CMOS inverter based on low temperature devices is the basic and essential component in digital circuits for the pressing applications such as wearable electronics and IoT technology. Although some hybrid CMOS inverters constructed by low temperature n-channel TAOS and p-channel poly-Si TFTs had been studied and realized, the electrical characteristics of TFTs were performed with high operation voltage, poor S.S, and large I OFF in these previous studies 18,19 . A conceptual VS hybrid CMOS structure consisted of BEOL compatible n-channel a-IWO NS-JLTs and p-channel poly-Si TFTs will be proposed and characterized in this work. The matched electrical characteristics of n-and p-channel devices with low operation voltage and low I OFF are exhibiting the promising candidate for future VS Hybrid CMOS applications.

Methods
The structure diagram of proposed BMG a-IWO NS-JLTs is schematically shown in Fig. 1(a). The proposed devices can be fabricated on Si wafers with 550-nm-thick buffer thermal SiO 2 or on glass substrates 16 . Firstly, a layer of 25-nm-thick Mo film was deposited subsequently by the direct current (DC) sputtering and patterned as the gate electrode through photolithography. Secondly, a layer of 10-nm or 20-nm or 30-nm-thick HfO 2 was deposited by atomic layer deposition (ALD) as the gate insulator (GI). Next, a layer of 4-nm or 10-nm-thick a-IWO channel was deposited by RF magnetron sputtering of an In-W-O (contained 4 wt.% of WO 3 ) ceramic plate target at room temperature. Then, the a-IWO channel active layer was patterned through photolithography. Thirdly, a layer of 25-nm-thick Mo film was deposited by DC sputtering and patterned as the source/drain (S/D) www.nature.com/scientificreports www.nature.com/scientificreports/ electrodes using the lift-off technique. Finally, after channel passivation processes, contact holes to the gate and S/D electrodes were patterned and opened through photolithography.
To investigate the influences of different GI materials on the devices, the a-IWO NS-JLTs in bottom Si-sub gate (BSG) configurations with a-IWO NS channel = 4 nm were also fabricated on a heavily doped n-type Si wafer with 30-nm-thick high-quality thermal SiO 2 GI, as shown in Fig. 1(b). Additionally, the low metal contamination Ni-induced lateral crystallization (LC-NILC) poly-Si TFTs with 50-nm-thick poly-Si channel and 10-nm-thick HfO 2 GI were also fabricated on Si-substrates to study the OFF-state electrical characteristics for VS hybrid CMOS applications. The detail LC-NILC processes were shown in our previous work 20 .  13 . The interfacial layer (IL) was consequently formed and found during deposition of HfO 2 GI on the channel in the conventional top-gate devices. Since the deposition of HfO 2 GI was made before the deposition of a-IWO NS channel in the proposed BMG a-IWO NS-JLTs, the IL between the HfO 2 GI and the a-IWO NS channel is negligible, resulting in near ideal S.S. and improved hysteresis characteristics 16 . Figure 2 exhibits the transfer characteristics of a-IWO NS-JLTs with different GI materials, different HfO 2 GI thickness, and different a-IWO channel thickness. In JL configurations, the doping or carrier concentration of the source/drain (S/D) and channel is uniform, heavy, and homogenous, which significantly reduces thermal budgets of processes and simplifies fabrication 5 . However, there are more negative V TH and worse subthreshold characteristics in JL devices with thicker thickness of channel (a-IWO channel = 10 nm) or under poorer gate controls (HfO 2 GI = 30 nm for BMG and SiO 2 GI = 30 nm for BSG) in Fig. 2 21 . Among these devices, the transfer characteristics of BSG a-IWO NS-JLTs with a-IWO channel = 4 nm and SiO 2 GI = 30 nm exhibit the weakest gate control on channel, resulting in the absence of an OFF-state within V GS = −2V ~ V GS = 2V. The ON-state currents (I ON ) and S.S. of BMG a-IWO NS-JLTs are enhanced by shrinking the HfO 2 GI thickness (HfO 2 GI = 10 nm) thanks to the better gate controllability. Although BMG a-IWO NS-JLTs with HfO 2 GI = 10 nm and a-IWO channel = 10 nm have the highest I ON and μ FE , the most positive V TH , highest I ON /I OFF , and steepest S.S. are accomplished in BMG a-IWO NS-JLTs with HfO 2 GI = 10 nm and a-IWO channel = 4 nm for low operation voltage applications. Therefore, we will focus the BMG a-IWO NS-JLTs with HfO 2 GI = 10 nm and a-IWO channel = 4 nm in the latter discussions.

Results and Discussion
In order to enhance the I ON , it is necessary to improve both of μ FE and the contact resistance (R C ) between S/D metal electrodes and TAOS channel. The normalized output characteristics of a-IWO NS-JLTs with (a) channel length (L) = 40 μm and (b) L = 5 μm are shown in Fig. 3. It is noted that as the thickness of HfO 2 GI scaling down from 30 nm to 10 nm, the driving currents of a-IWO NS-JLTs with 10-nm-thick HfO 2 GI operated at gate overdrive voltage (V GS − V TH ) = 2V are enhanced more than 3 times of magnitude compared with the one with 30-nm-thick HfO 2 GI. The significant enhancements in driving currents are attributable to the improvements in R C between the S/D metal electrodes and the a-IWO NS channel.
Transmission line model (TLM) measurement can be used to extract the R C of metal-semiconductor junction 22 . Figure 4  www.nature.com/scientificreports www.nature.com/scientificreports/   Fig. 4(c), when S/D electrodes contact with a-IWO NS layer, the R C related to Schottky barrier between S/D metal electrode and a-IWO NS channel is formed. Since the potential energy of a-IWO NS channel at S/D electrodes contact can be modulated by the gate voltage, the Schottky barrier becomes narrower as the gate voltage increases, as shown in Fig. 4(d). Higher vertical electric-field enhances more electrons tunneling behavior in addition to thermionic electron injection 23 . The R C is decreased with increasing gate voltage and scaling down the thickness of HfO 2 GI, resulting in higher I ON . The electrical mechanism can be summarized that the increase of the gate voltage will decrease the Schottky barrier height and make Schottky barrier narrower, resulting in the significant reduction of the value of R C . If a positive gate voltage is applied, it will modify the Fermi level in a-IWO NS layer and make the a-IWO NS channel more conductive and resultantly decreasing channel resistance (R ch ). The vertical electric-field enhanced by scaling down the thickness of HfO 2 GI also reduces the R C at the metal-semiconductor interface.
It is well known that the poly-Si transistors are BEOL compatible devices for three-dimensional integrated circuits (3-D ICs) applications 4-6 . The low-temperature BEOL TAOS TFTs and poly-Si TFTs are the suitable platforms enabling monolithic 3-D integration with hybrid CMOS technologies. One of the major challenges to integrate the TAOS and poly-Si-based CMOS technologies is on their mismatched operation voltages (V DD ) 24 . For a low and matched operation voltage, the small S.S and real I ON /I OFF under small gate operation voltage are critical. Figure 5 displays transfer characteristics of a-IWO NS-JLTs with different channel lengths. The extracted V TH roll-off of a-IWO NS-JLTs with different channel lengths is also plotted in the inset of Fig. 5. As the channel length scaling down, the V TH roll-off is a key parameter to verify the gate controllability over the channel region. The a-IWO NS-JLTs with different channel lengths have almost identical S.S. ~63 mV/dec. and similar I OFF characteristics, where the I ON is nearly proportional to channel length. Thus, the value of I ON /I OFF larger than 1 × 10 9 can be obtained for the device with 5 μm channel length at an operation conditions of V GS − V TH = 3V and V DS = 0.1V. The a-IWO NS-JLTs with very small V TH roll-off exhibit high gate controllability and good SCEs immunity thanks to the combined use of 2D-like a-IWO NS channel and thinner HfO 2 GI in devices.
For VS hybrid CMOS applications, the real I OFF under large drain operation voltage is the key parameter. The transfer characteristics of a-IWO NS-JLTs with W/L = 80 μm/5 μm and n-channel LC-NILC poly-Si TFTs with W/L = 40 μm/5 μm are shown in Fig. 6(a,b), respectively. In this work, the μ FE of n-channel LC-NILC poly-Si TFTs is about twice as high as that of a-IWO NS-JLTs. In order to achieve electrically-matched I ON , a wider channel width for the a-IWO NS-JLTs was studied. As shown in Fig. 6(a), the I OFF of a-IWO NS-JLTs with W = 80 μm operated at V DS = 0.1V and V DS = 1V, respectively, are almost identical and smaller than the measurement detection limit (~10 −13 A). The a-IWO NS-JLTs with near ideal S.S. can be operated at low voltage. The extremely high I ON /I OFF ~ 10 10 at V GS − V TH = 2.5V and V DS = 1V is accomplished in a-IWO NS-JLTs by virtue of the wide bandgap InO x -based NS channel. However, the n-channel LC-NILC poly-Si TFTs always suffer from higher gate-induced drain leakage (GIDL) currents and higher I OFF (=I min at V DS = 1V) due to poly-Si film with small bandgap and grain boundaries, resulting in poorer I ON /I OFF ~ 10 8 at V GS − V TH = 2.5V and V DS = 1V shown in Fig. 6(b). The a-IWO NS-JLTs with near ideal S.S., lower GIDL, and higher I ON /I OFF are more suitable for low-power VS hybrid CMOS applications compared with the n-channel LC-NILC poly-Si TFTs.  www.nature.com/scientificreports www.nature.com/scientificreports/ The technology potential for low-temperature processes applications on a glass substrate had been demonstrated 16 . In JL devices, the path of current transport is concentrated in the center of heavy uniform doping channel, which reduces the effects at the oxide/channel interface, resulting in near ideal subthreshold characteristics 6 . It is well known that μ FE is significantly decreasing as scaling channel thickness. The proposed 2D-like BMG a-IWO NS-JLTs with μ FE ~ 25.3 cm 2 /V-s exhibit near ideal S.S. and improved hysteresis characteristics because of the NS channel, JL configurations, and the good interface characteristics between the HfO 2 GI and the a-IWO NS channel 16 .

Conclusion
In summary, we have studied the influences of the different GI materials and the scalings of GI thickness, a-IWO NS channel thickness, and channel lengths on the electrical characteristics and performances of the 2D-like a-IWO NS-JLTs. Since a-IWO NS-JLTs are fabricated by using Ga-free a-IWO thin films, the material costs can be minimized compared with typically adopted a-IGZO. The Ga-and Zn-free a-IWO NS channel layers with low cost, high mobility, and good stability could be a promising alternative to a-IGZO for the advanced oxide-based TFT technology. Also, the 2D-like BMG a-IWO NS-JLTs significantly minimize the IL thickness, resulting in near ideal S.S. and improved hysteresis characteristics. The 2D-like BMG a-IWO NS-JLTs with small V TH roll-off, large I ON /I OFF , near ideal S.S., high μ FE , low R C , and low operation voltage appears highly promising potentials for system-on-panel (SoP) and VS hybrid CMOS applications in the future.