Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs

Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (Vd = 10 mV) and current drive up to 40 μA/wire (Vd = 0.3 V, diameter d = 50 nm) while dimensions including core diameter d, shell thickness and gate length are scaled towards CMOS requirements. The experimental data in conjunction with TCAD modeling reveal interface trap density requirements to reach industry standard off-current specifications.

Scientific REPORTS | (2019) 9:202 | DOI: 10.1038/s41598-018-36549-z traps within the band gap of InAs at the high-k/InAs interface and subsequent thermal emission into the InAs conduction band limits S to typically 110 mV/dec or greater at V d = 0.3 V. We then calculate the required D it limits in order to achieve industry standard off-current requirements for CMOS technology. Finally, the impact of GaSb core doping is shown and found to be a critical parameter necessary for high drive current.

Results and Discussion
C-S GaSb/InAs NWs were grown by metal organic chemical vapor deposition (MOCVD) using the vapor liquid solid (VLS) method from Au particle catalysts in predefined locations on an InAs substrate. Figure 2a shows a SEM image of a NW following MOCVD growth. A 300-400 nm long Sn-doped n-type InAs segment is first grown, followed by approximately a 20 nm long undoped GaAs segment, and 300-400 nm long Zn-doped p-type GaSb segment. The diameter of the InAs stem ranges from 23-32 nm and the GaSb core diameter ranges from 35-60 nm. Subsequently, an undoped InAs shell of approximately 3-5 nm is grown over the entire structure. To our knowledge, these are the narrowest C-S TFET structures reported. Even further diameter scaling of the nanowires towards CMOS relevant dimensions is possible and demonstrated for nanowires grown with Au colloids. The supplementary information includes grown GaSb-InAs C-S nanowires with GaSb core diameter of 17 nm and InAs shell of 3 nm. Further description of the growth process is outlined in the methods section. VGAA NW GaSb-InAs C-S TFET devices, as shown in Fig. 1, were fabricated using the process flow also described in the methods section below. Further detail of the device structure is shown in Fig. 2b-d, high-angle annular dark-field scanning transmission electron microscopy (HAADF STEM) images of a fabricated device and energy-dispersive x-ray spectroscopy (EDX) mapping of the constituent elements of the NW. The EDX spectra reveal the presence of an InAs shell and GaAs barrier layer. The images also confirm the InAs shell is removed in the region above the gate metal and is approximately 4.5 nm or less. Figure 3 shows I d − V g and S − I d of a single NW device with GaSb core diameter approximately 35 nm. At V d = 10 mV, minimum subthreshold swing equals 50 mV/dec, below the thermal limit for a MOSFET at room temperature. S is less than 60 mV/dec for approximately 2 orders of magnitude in drain current with I 60 = 1.5 nA/ wire. I 60 is defined as the current at which S increases above 60 mV/dec, and is desired to be as high as possible in order for the steep subthreshold swing to be technologically relevant. As V d increases from 10 mV to 300 mV, the off-state current increases to 1.4 nA/wire and S increases to 110 mV/dec. The V d dependence of S requires further experimental verification with additional structural modifications, which was not studied in this work. A possible mechanism for the increase of S is drain leakage due to the overlapped gate and drain. This could be studied by the addition of a bottom spacer in the device. The current drive at V d = 0.3 V, V g = 0.5 V is 4.3 μA/wire or 39.4 μA/μm normalized to GaSb core diameter of 35 nm. For the majority of fabricated devices, including the above, gate leakage is at the measurement noise floor. In Fig. 4, the output characteristics show asymmetry with drain voltage, though NDR is not observed at room temperature. However, reduction of the temperature to 10 K reveals the presence of NDR, confirming tunneling operation in the device.
Further devices measured also display S < 60 mV/dec at V d = 10 mV. The steepest S measured was found to be 40 mV/dec at V d = 10 mV. This is the steepest reported S for a core-shell TFET architecture. Figure 5 shows the I d − V g including hysteresis. Distinct steps are observed in the current, particularly for the down sweep. Similar steps were observed in axial TFETs 16 and were attributed to oxide defects. The minimum subthreshold swing in between the steps is approximately 40 mV/dec, however the steps degrade the average swing over one decade in current from 42 to 56 mV/dec. Core-Shell TFET On Performance. C-S TFETs have been thought to be attractive due to the line tunneling nature of the device, which should provide enhanced current drive. On current up to 27 μA/wire at V d = 0.3 V and I off = 1 pA/wire is predicted by atomistic simulation for an optimized GaSb-InAs C-S TFET with GaSb diameter of 6.6 nm 10 . Experimentally, the device with highest measured drive current and transconductance is shown in  In this case, drive current up to 40 μA/wire at V d = 0.3 V for a device with 50 nm GaSb core diameter is measured for V g = 2.5 V. The large gate overdrive necessary is consistent with having high D it (to be discussed later) and a large effective oxide thickness (EOT) of 3.5 nm. The EOT is calculated assuming an AlO x dielectric constant of 9 and thickness of 8 nm. In addition, there is no engineered alignment in energy of the InAs shell conduction band over the GaSb with respect to that over the GaAs barrier, as predicted to be necessary by atomistic simulation for a steep turn on of line tunneling 10 . This will add to the necessary gate overdrive. Comparing to the predicted value from atomistic simulation 10 , the measured current drive is approximately a factor of 5-38x less, dependent on an assumption of current to either scale linearly with the GaSb diameter or with the square of the GaSb diameter. The discrepancy is most likely due to insufficient GaSb doping (to be discussed later). The GaSb doping concentration used in the atomistic simulations is 1 × 10 20 cm −3 . For comparison with previously demonstrated C-S NW GaSb-InAs TFETs, Dey 15 reported a maximum current of approximately 8 μA/wire at V d = 0.3 V, V g = 1.5 V for a similar GaSb core diameter. Note that this device also turned off poorly, with the minimum measured current approximately 0.
Comparing to the InAs/GaAsSb/ GaSb axial TFET 5 with GaSb diameter of approximately 70 nm, the maximum current reported is approximately 4 μA/wire at V d = 0.3 V for V g = 0.5 V. Thus, the present devices demonstrate for the first time the current-drive capability of the core-shell architecture, although further improvements or changes to the device (discussed later) are necessary to simultaneously achieve the high current drive with steep S. . In (c) it is evident the InAs shell is etched in the region above the gate metal by the reduction of the NW diameter. In the EDX spectra, the brighter In and As signals at the edges of the NW also reveal the presence of a shell. The GaAs segment is also evident and is approximately 24 nm long.
Scientific REPORTS | (2019) 9:202 | DOI:10.1038/s41598-018-36549-z Verification of Radial Core-Shell Transport. In order to verify if the observed current was flowing through the InAs shell rather than axially across the GaAs barrier, reference devices were fabricated which were grown intentionally without an InAs shell. These devices provide a direct measure of the axial leakage across the GaAs barrier. Reference devices were fabricated with the same process flow, with appropriate modifications to account for the lack of InAs shell. Fig. 7a shows a plot of I max versus I min at V d = 0.3 V for a population of devices intentionally grown without shell and another with shell grown for 3 min. I max and I min are defined as the maximum and minimum measured current within the measured gate-voltage range. Each point is measured with the same gate-voltage range.
Clearly, there is a difference of greater than 100 × in current levels for the two populations. This confirms transport is occurring within the shell in the C-S TFET devices. Fig. 7b shows example I d − V g curves for a device from each.

Off Current and Subthreshold Swing Limits.
To further investigate the off-current and subthreshold swing limitations, temperature dependent measurements were performed from room temperature down to 10 K. Fig. 8 shows temperature dependent There is a large temperature dependence, particularly in the off and subthreshold regime. The minimum current reduces to the noise floor near 200 K, and the minimum subthreshold swing reduces with temperature down to 15 mV/dec at 10 K. The  gate leakage (not shown) is at the noise floor for all measurements. An activation energy, E a , was also extracted by constructing an Arrhenius plot of the natural log of the current versus 1/kT. Fig. 8b shows E a versus gate voltage. E a has a peak value of 0.41 eV at zero gate bias and reduces as the gate bias increases to nearly 0 eV in the on state.
In the on state, the low activation energy is an indication of band-to-band tunneling 17 . E a also reduces for more negative gate voltage in the region where the current starts increasing with additional negative gate bias. This might be explained by ambipolar tunneling current in the InAs drain.
To further understand the physical mechanisms for the observed temperature dependence, Sentaurus Device 18 (s-device) was used to model the device structure. The details of the simulation can be found in the supporting information. A Gaussian D it distribution with peak at 1.4 × 10 13 cm −2 eV −1 centered at the InAs conduction band edge (E c ) and at the high-k/InAs interface was included to account for defects in the device. This D it distribution is similar to experimentally obtained values for InAs with similar surface treatment prior to high-k deposition and high-k 19 . Other defects, such as traps at GaSb-InAs, GaSb-GaAs, or GaAs-InAs interface were not included as none were observed in TEM. In addition, NWs are known to accommodate lattice mismatch without generation of defects 20 . Fig. 9 shows I d − V g of the simulated device, both ideal and with traps included compared to the measured curve, and an energy band diagram to aid in understanding the trapping mechanism. When comparing the ideal with the measured curve, it is obvious the effect of traps is significant and must be included to predict the measured current. The device with traps has a degraded subthreshold swing and a plateau in the off state. The D it contributes an electrostatic degradation of the subthreshold swing, but the more dominant degradation is the trap-assisted tunneling current generated due to the presence of traps. The mechanism of trapping is understood with help from the energy band diagram in b), a cut perpendicular to the gate in the channel region. Electrons in the valence band of GaSb tunnel into empty trap states in the energy gap of InAs at the high-k/InAs interface and subsequently are thermally emitted into the conduction band. This process gives rise to a trap-assisted tunneling current. It is worth noting that this TAT process should be NW core diameter independent for the same InAs shell and high-k thickness. This is consistent with similar measured S values over a large number of devices of approximately 110-150 mV/dec at V d = 0.3 V for both 35 and 50 nm GaSb core diameter devices.
It is now apparent that to improve subthreshold swing and reduce off current in experimental devices, mitigation or reduction of D it is critical in order to suppress trap-assisted tunneling current. To estimate the required D it necessary to reduce TAT current and reach specified off-current levels, the magnitude of D it was varied in s-device simulations. To reach an off-current requirement of 100 pA/wire, a D it ≤ 10 12 cm −2 eV −1 is calculated. D it ≤ 10 12 cm −2 eV −1 has been previously reported for example, by using an oxygen-terminated InAs surface 21 .
To reach an off-current requirement of 1 pA/wire, a D it ≤ 10 10   In addition, devices with 1× flow exhibit source depletion effects in the I d − V g curve as seen in Fig. 10b. Most pronounced at low drain bias (due to the additional effect of saturation of the energy windows available for tunneling that is more pronounced at low drain bias 23 ), the current peaks and then reduces as gate bias increases. This occurs because the gate bias depletes the GaSb due to insufficient doping, which increases the barrier length for tunneling. GaSb doping is thus a critical parameter in a C-S TFET device and must be sufficiently high to obtain high current levels. Fig. 10c further illustrates the importance of having sufficiently high GaSb doping. Relative on current versus GaSb doping concentration was simulated with s-device. On current reduces by orders of magnitude if the doping is not sufficient. The doping requirements also depend on GaSb core diameter and are higher as the diameter is reduced.

Conclusions
GaSb-InAs C-S TFETs are promising candidates for a low-voltage CMOS technology due to their high current drive capability. We have advanced the experimental state and demonstrated the first VGAA NW GaSb-InAs C-S TFETs and have shown key properties and physics with S down to 40 mV/dec at V d = 10 mV and room temperature, drive current capability up to 40 μA/wire at V d = 0.3 V, NDR, transport through the InAs shell, and GaSb

Methods
MOCVD Growth of Core-Shell Nanowires. NWs are grown in VLS mode from Au particle catalysts.
In VLS growth, a vapor-phase precursor catalytically decomposes at a metal nanoparticle surface, forming a supersaturated eutectic liquid. The solid crystalline nanowire grows by precipitation from the liquid catalyst particle. To form the Au particle catalysts, e-beam lithography was used to pattern holes in resist of 15 or 20 nm in diameter on an InAs 111B substrate with n-type sulphur doping = 1 × 10 18 cm −3 . 15 nm of Au was e-beam evaporated and standard lift-off was used to define Au particles in pre-defined positions. NW growth took place in an Aixtron CCS closed coupled showerhead MOCVD reactor. Purified hydrogen with a total flow of 8 l/min was used as carrier gas. The precursors used for growth of the NWs were trimethylindium (TMIn), arsine (AsH 3 ), and tetraethyltin (TESn) for InAs and trimethylgallium (TMGa), trimethylantimony (TMSb), and diethylzinc (DEZn) for GaSb. The V/III ratio during growth of GaSb was controlled by an Epison feedback controller. The reactor temperature was calibrated by means of a LayTec EpiR TT in-situ metrology system. The epitaxy started  with a thermal annealing step at 500 °C. Meanwhile the substrate was stabilized by an AsH 3 flow of 20 ml/min at 100 mbar reactor pressure. After annealing, the susceptor temperature was set to the InAs growth temperature of 460 °C. When the correct growth temperature was attained and stabilized for about 3 minutes InAs NW growth commenced. The InAs(Sn) NW was grown for about 3 minutes then growth was stopped and the reactor temperature was raised to slightly above 500 °C in an AsH 3 flow. When the reactor temperature was stable AsH 3 was switched to TMSb followed by the addition of TMGa and DEZn. During this sequence of switching, the growth interrupt time between AsH 3 turn off and TMGa turn on controls the degree to which a GaAs segment forms due to residual AsH 3 in the growth chamber. Since a GaAs segment is desired in the structure, the interrupt time was kept short. The GaSb(Zn) segment was grown for 15-20 minutes. Finally, the temperature was lowered and an undoped InAs shell was grown for 3-4 minutes.

Data Availability
Data generated or analyzed during this study are available from the corresponding author upon reasonable request.