Large current modulation and tunneling magnetoresistance change by a side-gate electric field in a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor

A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current IDS modulation by a gate-source voltage VGS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large IDS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that IDS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by VGS. This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

measured to be 4 mΩ.cm, 10 mΩ.cm and 5.8 μΩ.cm, respectively, using Hall-bar structures. The modulation of resistance in the GaAs:Be layer by a gate electric field was also measured to be ~3% at 3.8 K using a Hall-bar structure with a gate electrode.
Because the carrier concentration of the GaMnAs layers and Au/Cr layers are much larger than that of the GaAs:Be layer, the modulation of resistance in the top and bottom GaMnAs layers and Au/Cr layers is expected to be much less than 3%. Considering that the drain-source resistance changes from 80 kΩ (at V DS = 200 mV) to 1.5 MΩ (at V DS = 5 mV) at 3.8 K (see the purple curve in Fig. S2), the modulation of the parasitic resistances is (1.6 mΩ + 0.5 mΩ + 20 mΩ + 10 µΩ)×3% / 80 kΩ ~0.8×10 -6 % at most, which is much smaller than the experimentally obtained value (~130% at V DS = 80 mV and V GS = -20 V). Thus, the influence of the gate leakage current and electric field effect on the parasitic resistances is negligibly small.

Supplementary Note 2. Details of the calculation of the electric potential profile and the normalized drain-source current in our vertical spin MOSFET
The device structure used in our simulation is shown in Fig. S1. To calculate the electric potential profile with various gate voltages, we solved the following two-dimensional Poisson equation.
Here, E V is the valence band top energy of GaAs in terms of hole energy, ρ is the charge density and is the dielectric constant of GaAs, respectively. Because all the experimental results presented in the main text were obtained at 3.8 K, activation of donors/acceptors and thermally excited carriers can be neglected in GaAs. Thus, we set the charge density at 0 in GaAs, meaning that the right side of Equation (S1) is 0.
Considering that the potential barrier height of GaAs is ~0.1 eV for holes in the GaMnAs layers, Equation (S1) is solved under the following boundary conditions.
Here, E F is the Fermi level, E V (S) is the valence band top energy with respect to E F at x = 0 (the interface between the side-gate electrode and GaAs), L is the channel length and W is the width of the calculated region [see Fig. S1].
As the boundary condition at the interfaces of GaMnAs/GaAs (y = 0 and L), we used the E V profile obtained for GaMnAs; in the surface depletion region of eV, which is the same as the barrier height of GaAs for holes, in GaMnAs. Considering the above conditions, the energy profile at y = 0 and L can be expressed by the following equation.
Here, N A is an acceptor concentration of GaMnAs and we set N A at 10 20 cm -3 . To introduce the effect of the gate electric field, we changed E V (S) . When a gate voltage is  Table S1. Equation (S1) was solved using Jacobi's iterative method so that the potential difference between the present step and the previous step at all (x, y) becomes less than 10 -9 eV. Each mesh is a rectangle with a width in the x direction (Δx) of 0.1 nm and a width in the y direction (Δy) of 0.1 nm.
The drain-source current I DS at E V (S) can be expressed by the following equation.
Here, W mesa is the width of our mesa (500 nm), V ( ) ( ) is the current density at x and E V (S) , L mesa is the length of our mesa (50 μm) and N mesa is the number of the mesas (10).
When the applied voltage between the source and the drain |V| is much smaller than the barrier height, the carrier energy E dependence of tunneling probability can be neglected. Thus, V ( ) ( ) can be described by Here, D top , D bot and Using equation (S4) and (S5), we can obtain the following relationship between I DS and V (S) ( ).
Note that we consider that D top and D bot do not depend on E V (S) . Therefore, only V (S) ( ) can be calculated using the Wentzel-Kramers-Brilluion approximation. The right side of Equation (S6) can be calculated as follows.
Here, , V (S) ( , ) is the valence band top energy at (x, y) and E V (S) and ħ is the reduced Planck constant.
Thus, the calculated I DS normalized at V GS = 0 V, corresponding to E V (S) = E g /2, (γ calc ) can be described as follows.  We show R DS vs. V DS at various temperatures in Supplementary Fig. S2. If I DS were dominated by direct tunneling, R DS vs. V DS characteristics would not depend on the temperature. In our vertical spin MOSFET, when the temperature was changed from 300 K to 3.8 K, R DS was changed from 2 kΩ to 1.2 MΩ at V DS = -10 mV. The strong temperature dependence of R DS is experimental evidence of the indirect tunneling via defect states.

Supplementary Note 4. Estimation of the Curie temperatures of the top and bottom GaMnAs layers.
To estimate the Curie temperature T C of the GaMnAs layers, we measured the temperature dependence of the major loop, as shown in Fig. S3. Here, the drain-source voltage V DS is -5 mV, the gate-source voltage V GS is 0 V and the external magnetic field H is applied along the [-110] direction. TMR was observed up to 20 K and disappeared at 30 K, as shown in Fig. S3. Thus, considering that the top GaMnAs layer has a higher T C than the bottom GaMnAs layer in GaMnAs / GaAs / GaMnAs systems, 3 the T C of the bottom GaMnAs layer is estimated to be ~30 K. To estimate the T C of the top 10nm-thick GaMnAs layer, we prepared another heterostructure composed of Ga 0.94 Mn 0.06 As (10 nm, the same thickness and the same Mn content) / GaAs (100 nm) on a semi-insulating (SI) GaAs (001) substrate using growth conditions similar to those for the top GaMnAs electrode of the GaMnAs/ GaAs/ GaMnAs sample described in our manuscript. We measured the temperature (T) dependence of the two-terminal resistance R of the GaMnAs layer using a patterned rectangular bar with a width of 25 μm and a length of 150 μm (the black solid curve in Fig. S4). The peak in the dR/dT -T characteristic (the red solid curve in Fig. S4) is known to correspond to the T C in the GaMnAs film. 4 Therefore, we can estimate the T C of the top GaMnAs layer to be ~53 K (indicated by the red arrow). Post-growth annealing was not carried out for the GaMnAs/ GaAs/ GaMnAs sample described in our manuscript. curve, left axis) and the derivative of R with respect to T, dR/dT (the red solid curve, right axis). For the measurement, a patterned rectangular bar with a width of 25 μm and a length of 150 μm is used. The bias current used for the measurements is 100 nA. The red arrow indicates the T C . The inset in Fig. S4 shows the schematic illustration of the heterostructure used for estimating the T C of the top GaMnAs layer.

GaMnAs-based vertical spin MOSFET.
To confirm whether the GaMnAs-based vertical spin MOSFET is fabricated properly or not, we took an optical microscope photograph of the device, as shown in Fig. S5. The comb-shaped drain electrode with 20 comb teeth is formed and the gate electrode is deposited on the comb-shaped drain electrode covered with the HfO 2 layer.