Modulating Thin Film Transistor Characteristics by Texturing the Gate Metal

The development of reliable, high performance integrated circuits based on thin film transistors (TFTs) is of interest for the development of flexible electronic circuits. In this work we illustrate the modulation of TFT transconductance via the texturing of the gate metal created by the addition of a conductive pattern on top of a planar gate. Texturing results in the semiconductor-insulator interface acquiring a non-planar geometry with local variations in the radius of curvature. This influences various TFT parameters such as the subthreshold slope, gate voltage at the onset of conduction, contact resistance and gate capacitance. Specific studies are performed on textures based on periodic striations oriented along different directions. Textured TFTs showed upto ±40% variation in transconductance depending on the texture orientation as compared to conventional planar gate TFTs. Analytical models are developed and compared with experiments. Gain boosting in common source amplifiers based on textured TFTs as compared to conventional TFTs is demonstrated.

: 4 datasets for plane and textured gate devices with channel length L = 15µm, each set consisting of transfer characteristics at V ds =0 to 2V in steps of 0.5V, output characteristics at V gs =0 to 10V in steps of 2.5V, transfer characteristics in log scale, derivative of transfer characteristics in log scale Figure S4: 4 datasets for plane and textured gate devices with channel length L = 40µm, each set consisting of transfer characteristics at V ds =0 to 2V in steps of 0.5V, output characteristics at V gs =0 to 10V in steps of 2.5V, transfer characteristics in log scale, derivative of transfer characteristics in log scale Variation of TFT parameters with the angle of texturing

Co-ordinate system for planar and textured cases
The polar and Cartesian co-ordinates are interrelated.  Figure S7: Illustration of the Co-ordinate system For planar devices: There is only an x − y coordinate system along channel length and channel width, respectively. The z-axis normal to the semiconductor-insulator interface is not used.

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For the textured device: We need the z-coordinate, but we prefer it in polar form (r, φ) with radial coordinate r, as it greatly simplies the electrostatic analysis. The texturing is along a θ direction as shown in Fig. S7 (please note that this is not the angular coordinate of the polar system) Therefore this is the co-ordinate mapping for texturing: Therefore, the c i (x, y) for an elemental section is also a c i (r, φ).
Derivation of surface potential, free carrier concentration and I-V characteristics of textured gate TFTs Solution to Poisson Boltzmann equation in polar coordinates Let α = r 2 e p ; β = r dp dr , dβ dα = dβ dr dr dα = dp dr + r d 2 p dr 2 1 2re p + r 2 e p dp dr = 1 r dp dr + d 2 p dr 2 r 2re p + r 2 e p dp dr Multiplying 2r 2 to Eqn. 2, 2r 2 d 2 p dr 2 + 2r dp dr − 2qn t0 r 2 e p s V tc = 0

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Subtract Eqn. 2 from Eqn. 5, 2r dp dr − 2r 2 d 2 p dr 2 + r 2 dp dr Multiply 1 r 2 dp dr to Eqn. 6, 2 r dp dr 2 − 2 dp dr d 2 p dr 2 + dp dr Eqn. 7 is modied to, 2 r dp dr 2 − d dp dr 2 dr + dp dr 3 = − C 1 r 2 dp dr Let dp dr 2 = z, Therefore, Using Wolfram symbolic dierential equation solver, the exact solution for this is : Since dp dr 2 = z, dp dr = ± 2 r κ tan κ ln The solution with the -sign does not satisfy Eq. 2, therefore p = 2 ln l c r sec κ ln r l b S-10 Here the constant of integration has been absorbed in the logarithm term to generate a constant coecient l c . Substituting Eqn. 9 in Eqn. 2, we get l c = κl tc where l tc = 2 s V tc /qn t0 . Therefore, The boundary conditions to be used are, According to the boundary conditions Eqn. 12 and Eqn. 13, we apply dp dr = 0, p = 0 at r = r c ± t s in Eqn. 5 to obtain, with the`+' and`-' signs used for concave and convex cases respectively.
Inorder to use the boundary condition given in Eqn. 14, we calculate the electric eld (ξ) from Eqn. 11 to be, In the boundary condition in Eqn. 14, the LHS represents the magnitude of charge at the insulator semiconductor interface, which is positive. We have used appropriate sign change on the RHS of the boundary condition to adapt to the geometric conventions that we have used. In our case r is positive in the radially outward direction, and ξ will be positive in concave case and negative with respect to r in convex case. Substituting the electric eld expression in Eqn.
16 at r = r c in the boundary condition given in Eqn. 14 yields, Also noting that l tc << r c , Using l tc << r c , κ can be approximated to be (r c ± t s )/l tc . Substituting for κ in the above expression yields, Since e ϕs/Vtc >> 1 > t s /r c , the above expression simplies to, The Eqn. 17 is in the form e x = ax + b, whose solution is given by the zero order Lambert W function as, In this case, a = −(l tc c i± )/ s and b/a = −(V gs −V f b )/(2V tc ). Therefore, the surface potential for concave and convex TFTs is given by, where`+' and`-' corresponds to concave and convex cases respectively. As Lambert W function can be approximated as W 0 (x) = ln(x) − ln(ln(x)) at high V gs , Neglecting ln( s /(l tc c i± )) in the second term, Using l tc = (2 s V tc )/(qn t0 ), the surface potential is given by, Here + corresponds to concave case and -corresponds to convex case. The insulator capacitance in a textured gate TFT will vary spatially depending on the curvature of the insulator semiconductor interface and will take values corresponding to planar, concave or convex cases, as discussed in the manuscript. Also, by referring all voltages to the source electrode, the surface potential can be expressed as In order to calculate l b , use ϕ(r − r c ) = ϕ s in Eqn. 11, e ϕs/2Vtc = κl tc r c sec κ ln r c l b κ ln r c l b = sec −1 r c κl tc e ϕs/2Vtc Since sec −1 can return both positive and negative values, we mention this explicitly by using a ± sign. Therefore, Using Eqn. 22 in Eqn. 11, we get the potential variation in the semiconductor to be, ϕ(r) = 2V tc ln κl tc r sec ± sec −1 r c κl tc e ϕs/2Vtc − κln r r c where + is for the concave case and -is for the convex case.

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Calculation of Free Carrier Concentration, N f Electrons available for conduction in the semciconductor = N f (/cm 2 ) Here n f = n f 0 e ϕ/V th and ξ is calculated from Poisson's equation. Therefore, Therefore, Case 1b: Therefore, Noting that, Therefore, Depending on the capacitance of concave or convex cases, the free carrier concentration also varies, according to the equation, γ tc polar = γ tc planar

I-V Characteristics
Current per unit width, Substituting for qN f = γ (c i (V gs − V on − V ch )) α and µ = µ 0 Integrating both sides, Therefore, the total drain current is given by, In the presence of contact resistance, Vgs at the onset of conduction for dierent channel lengths