Figure 2 | Scientific Reports

Figure 2

From: Near-Zero-Power Temperature Sensing via Tunneling Currents Through Complementary Metal-Oxide-Semiconductor Transistors

Figure 2

Architecture of the proposed temperature sensor. (A) A temperature-stable current source was employed to generate a CWT ramp voltage, V ramp , CWT , by charging capacitor C REF . (B) A PTAT current source was employed as the temperature sensing core by converting temperature to a corresponding current and generated a PTAT ramp voltage, V ramp, PTAT , by charging a digitally-controllable bank of capacitors C DAC . (C) An analog processing unit consisting of a temperature-stabilized VRG, comparators, and an arbiter was implemented to translate the temperature-encoded analog voltages to digital signals. (D) Schematic of the Arbiter. (E) A digital processing unit processes the information, controls C DAC , and generates the digital codes corresponding to the ambient temperature. (F) An example operation of the DPU illustrates that C DAC was tuned via discrete time digital feedback to match the rising time of V ramp, CWT in RSU.

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