High-Gain Graphene Transistors with a Thin AlOx Top-Gate Oxide

The high-frequency performance of transistors is usually assessed by speed and gain figures of merit, such as the maximum oscillation frequency f max, cutoff frequency f T, ratio f max/f T, forward transmission coefficient S 21, and open-circuit voltage gain A v. All these figures of merit must be as large as possible for transistors to be useful in practical electronics applications. Here we demonstrate high-performance graphene field-effect transistors (GFETs) with a thin AlOx gate dielectric which outperform previous state-of-the-art GFETs: we obtained f max/f T > 3, A v > 30 dB, and S 21 = 12.5 dB (at 10 MHz and depending on the transistor geometry) from S-parameter measurements. A dc characterization of GFETs in ambient conditions reveals good current saturation and relatively large transconductance ~600 S/m. The realized GFETs offer the prospect of using graphene in a much wider range of electronic applications which require substantial gain.

Graphene is one of the most intensively investigated two-dimensional materials for electronics owing to its large charge carrier mobility (>5,000 cm 2 /(Vs) at room temperature) 1 , which is almost equal between holes and electrons 2 , and large saturation velocity 3 . However, despite intensive research efforts, there are no graphene-based electronic devices available on the market at present. The lack of a bandgap in graphene prevents GFETs from being turned off, which results in large off-state currents and high static power dissipation, and thus represents a fundamental obstacle for the development of graphene-based logic gates 4 .
In contrast, turning off transistors is not required for most analog applications, but the absence of a bandgap weakens the drain current saturation required for high gain operation. Therefore, improving current saturation in GFETs in combination with high mobility of graphene, represent a promising path in the field of high-frequency analog electronics. One possible way to improve current saturation in GFETs is to use ultra-clean samples exhibiting high saturation velocity on substrates with high phonon energy and small density of defects, e.g., h-BN 5 . However, this technology is not yet mature enough to be applied in a large-scale production and is limited by the high cost and complex processing. Similarly, patterning graphene into nanoribbons to open a bandgap reduces the charge carrier mobility and therefore the on-state current, eliminating advantage of improved current saturation. A different approach consists of using thin gate dielectrics in order to assist the channel "pinch-off " and reduce the effect of intrinsic carriers and interfacial traps, which consistently improves saturation 6 . A thinner oxide (thickness t ox ) also improves the transconductance (g m ) which is proportional to − t ox 1 . Here we demonstrate high-frequency GFETs on conventional SiO 2 substrates with improved drain current saturation yielding high-gain operation. The current saturation was improved by utilizing a thin (t ox ~ 4 nm) AlO x top-gate insulator with good dielectric constant (ε r,ox ~ 6.4). This resulted in improved oxide capacitance (C ox = 1.37 μF/cm 2 ) 7, 8 and therefore strong gate control over carriers in the graphene channel. As a consequence, the output conductance (g d ) was reduced well below 50 S/m (normalized by the channel width W) leading to very large values of the open-circuit voltage gain A v > 30 dB and forward gain S 21 = 12.5 dB (at 10 MHz) in GFETs with the channel widths W = 10 μm and W = 100 μm, respectively, which are the highest gains measured in GFETs so far [9][10][11][12] . This low output conductance also contributed to a large ratio between the extrinsic maximum oscillation frequency (f max ) and cutoff frequency (f T ) of ~3, which is unusually high for GFETs, in which f max /f T typically Scientific RepoRts | 7: 2419 | DOI:10.1038/s41598-017-02541-2 ranges from <1 13, 14 to ~1.5 15, 16 to 3.3 17 . However, the highest measured extrinsic f max was 21.3 GHz highlighting the need for alternative substrates with less charge traps 14 and cleaner graphene transfer process 16 .
GFETs comprising the same type of gate insulator have been successfully implemented in the past in more complex circuits like integrated inverters and ring oscillators capable of performing signal generation up to 4.3 GHz 18 , voltage gain up to 13 or 22.3 dB 19 , mixing and modulation 7 . However, a direct investigation of the high frequency performance of these GFETs has not been performed so far. In this work, different figures of merit, such as f max , f T , A v and S 21 , were extracted from the S-parameter measurements of the individual GFETs to investigate their performance and scaling.

Experimental
Monolayer graphene grown by chemical vapor deposition (CVD) on Cu was used in the fabrication of the investigated coplanar GFETs. After the growth, graphene was transferred to high-resistivity (~5 kΩcm) Si substrates with a 1 μm thick top layer of SiO 2 by a wet process 4 . The graphene stripes were defined by e-beam lithography followed by reactive ion etching in oxygen plasma. The coplanar GFETs were fabricated as depicted in Fig. 1. The channel width W was 10, 40 and 100 μm while the gate length L was 0.8, 0.9, 1, 1.1 and 2.2 μm. Top gates were patterned by e-beam lithography followed by e-beam evaporation of 100 nm of Al. A thin (t 4 ox nm) native layer of AlO x was formed on all surfaces of the Al gates (including the surface at the interface with graphene) by exposing the samples to air 8,[20][21][22][23] . The source/drain contacts were fabricated in the final e-beam lithography step, separated by a very small underlap (u ~ 100 nm) from the gate. Such underlaps introduce access resistances between the source/drain and gate which cannot be gated and therefore reduce transconductance and gain. The access resistances can be eliminated by a self-aligned transistor layout 4,21 in which the source and drain are overlapped with the gate. However, we found that overlaps introduce additional parasitic capacitances which have more detrimental effect on the high-frequency response of the transistors than access resistances. Typically, self-aligned GFETs with overlapped gate and source/drain exhibited ~3 times smaller f max compared to GFETs with (small) underlaps. Such deterioration of the high-frequency response has not been observed in self-aligned T-gate GFETs on flexible substrates 23 . This is probably because the sufficiently large underlaps have been created by shadowing the evaporated source/drain material by the T-gates 23 . The source/drain contacts were made of Au (100 nm thick, without an additional adhesion layer) because we found that pure Au 7 provides the lowest contact resistance to graphene (~250 Ωμm) among the several tested metal combinations (e.g., Ti/Au, Ni/Au, Pd/Au).

Results and Discussion
All GFETs were initially characterized at dc to find the optimum biasing conditions for the S-parameter characterization. In ambient air, most of the fabricated GFETs exhibited p-type behavior at low biases with the Dirac voltage . V 0 25 0 V. A small hysteresis was observed in the dc characteristics of the GFETs. The shift of the Dirac voltage was ~12% of the V GS sweeping range and it did not have any influence on g m and g d . We found that the transconductance of the GFETs was larger in the p-type regime (V GS < V 0 ) than in the n-type regime (V GS > V 0 ). This can be attributed to the larger contact resistance in the n-type regime due to the formation of a "pnp" junction between the large workfunction Au contacts and the n-type channel 24, 25 . Moreover, the hole mobility was also found to be slightly larger than the electron mobility, as expected for graphene deposited on SiO 2 substrates 26,27 . Therefore, the GFETs were biased in the p-type regime to maximize the transconductance during the S-parameter characterization. In order to also minimize the output conductance, the GFETs were measured in the p-type saturation regime (V DS < V GS − V 0 < 0). S-parameter measurements were performed in a Cascade Microtech Summit 12561B probe station. Input and output ac signals were applied by Anritsu Vectorstar MS4647A vector network analyzer. Gate and drain dc biasing was applied by Keithley 2600 source meters. The GFETs were probed by Cascade Microtech 110-A probes with a 100 μm-pitch. Figure 2 shows the output characteristics and conductance of a typical GFET with L = 1 μm and W = 10 μm for several negative values of V GS , i.e., for transistor operation deep into the p-type regime. Additional advantage of operating p-doped GFETs in the p-type regime is that larger drain currents I D can be reached compared to the n-type regime. This is because larger values of − V V GS 0 for V 0 > 0 can be obtained for negative V GS than for positive V GS since |V GS | is limited by the breakdown voltage V b of the gate oxide (here V b = 2.9 V). At small V DS , the graphene channel is uniformly p-doped and the GFET is in the ohmic regime exhibited by the linear I D − V GS curves. A larger V DS reduces the hole concentration near the drain leading to charge neutrality and the onset of saturation at = − V V V DS GS 0 . At even larger V DS , the charge neutrality point moves towards source with electron accumulation on the drain side. However, as long as V DS is not too large, the electron accumulation is not significant and the output conductance approaches zero reflecting strong current saturation. In this regime, the thin dielectric exerts strong capacitive control over the drain current leading to a larger channel depletion rate which improves the drain current saturation 6 0 , the current saturation is lost due to significant  Fig. 3(a). The gain was extracted from the S-parameter measurements of the GFETs biased at negative V DS and V GS . The open-circuit voltage gain is equal to the intrinsic transistor gain = A g g / m d at low frequencies. The intrinsic gain A is not expected to scale with W or L because g m scales with W/L while g d approximately scales with W/L. However, due to the influence of the contact resistance, the intrinsic gain A and consequently A v were smaller at shorter L. The largest measured A v was above 30 dB at 10 MHz for GFETs with L 1 μm and W = 10 μm. This is the highest voltage gain reported for GFETs so far [9][10][11] . The notable scatter of gain values can be attributed to device-to-device variability from the intrinsic non-uniformity of CVD graphene and contact misalignment. Due to the inherent overlay error of the e-beam exposure system, the perfect alignment between the gate and source/drain contacts, as shown in Fig. 1(c), was not possible in all fabricated GFETs. This led to the scatter in the measured data because, e.g., smaller underlap (or even unintentional overlap) reduced access resistances and therefore increased A v and S 21 , but at the same time reduced f T and f max due to the increase of parasitic capacitances.
The measured forward transmission coefficient S 21 as a function of W L / is shown in Fig. 3(b). This coefficient reflects the real power amplification as S 21 2 is equal to the transducer power gain of a two-port network. We found that S 21 scales with W L / which was expected as it is proportional to g m . The narrowest devices (W=10 μm) exhibited < S 0 21 dB, i.e., power attenuation. The highest measured value was 12.5 dB at 10 MHz for 10 times wider devices. This is also the highest S 21 reported in literature for a graphene channel with W=100 μm 12 . Figure 4(a) shows the cutoff frequency f T measured on each GFET and plotted as a function of the gate length L. The highest measured f T was 10.3 GHz in a device with W = 10 μm and L = 1 μm. The cutoff frequency is strongly affected by relatively low charge-carrier mobility (μ < 1000 cm 2 /(Vs)). Mobilities above 5000 cm 2 /(Vs) have been obtained in CVD graphene deposited on SiO 2 26,27 , but the top gate introduces charge traps at the interface with graphene that act as scattering centers degrading transistor performances. The cutoff frequency f T was found to scale approximately with − L 1 , as suggested by the black line in Fig. 4(a). However, the scaling trend is not preserved at submicron gate lengths due to the increased influence of contact resistance in shorter devices. Figure 4(b) shows the highest measured maximum oscillation frequency f max obtained for each GFET and plotted as a function of the gate length L. The highest measured extrinsic f max was 21.3 GHz in a GFET with W = 10 μm and L = 1 μm (discussion on the intrinsic f max can be found in the Supplementary information). The obtained values are comparable to those of GFETs with the same gate length 14,16,28 . Even though it has previously been found that f max does not scale very well with the gate length in GFETs 28 , we observed a gate-length dependence − L 1 down to 0.8 μm, despite noticeable degradation in submicron devices. We obtained larger f max in narrower devices confirming expected scaling 1 /2 , where R g is the gate resistance 28 . Even larger f max can be obtained if the contact and gate width are adjusted to the actual channel width (i.e., not as in the presented GFETs in which the same metal layout shown in Fig. 1 was used regardless of the channel width). In such devices, the highest measured f max was 26 GHz with W = 10 μm and L = 1 μm. However, in general, narrower channels result in smaller gain S 21 , i.e., there is a tradeoff between S 21 and f max . Figure 5 shows the maximum oscillation frequency f max as a function of the cutoff frequency f T . Larger ratio f f / max T usually indicates better drain current saturation because, to a first approximation,  29 . In most of the GFETs realized so far, f max is usually smaller than f T 13,14 . A ratio of 1.5 has been obtained in GFETs by reducing the gate resistance through a T-gate structure 15,16 . The highest ratio reported so far in GFETs has been 3. 3  GHz was obtained at a gate length = L 1 μm indicating adverse influence of contact resistance at shorter gate lengths. However, the critical technological parameters that should be optimized to improve f max have been identified and they are mostly technological rather than fundamental in nature. The quality of CVD graphene should be enhanced to provide better homogeneity, allowing a more accurate study of the improvement of transistor performance with scaling. Smoother substrates and less defective interfaces should be used to reduce the scattering and increase carrier mobility. Contact resistance should be reduced below 100 Ωμm to simultaneously improve gain and frequency performances. Finally, the gate resistance should be reduced to enhance f max , which can be accomplished through a T-gate structure. Our study has therefore also served to emphasize several remaining challenges of graphene technology which should be overcome to further expand applications of GFETs in electronics.