Remarkably High Mobility Thin-Film Transistor on Flexible Substrate by Novel Passivation Material

High mobility thin-film transistor (TFT) is crucial for future high resolution and fast response flexible display. Remarkably high performance TFT, made at room temperature on flexible substrate, is achieved with record high field-effect mobility (μ FE) of 345 cm2/Vs, small sub-threshold slope (SS) of 103 mV/dec, high on-current/off-current (I ON/I OFF) of 7 × 106, and a low drain-voltage (VD) of 2 V for low power operation. The achieved mobility is the best reported data among flexible electronic devices, which is reached by novel HfLaO passivation material on nano-crystalline zinc-oxide (ZnO) TFT to improve both I ON and I OFF. From X-ray photoelectron spectroscopy (XPS) analysis, the non-passivated device has high OH-bonding intensity in nano-crystalline ZnO, which damage the crystallinity, create charged scattering centers, and form potential barriers to degrade mobility.

, where C G and f are the gate capacitance and operation frequency, respectively. This remarkably high mobility TFT is achieved using novel HfLaO passivation on nano-crystalline ZnO. For comparison, the control non-passivated device has a μ FE of 43 cm 2 /Vs. To understand such large mobility improvement, the X-ray photoelectron spectroscopy (XPS) was performed. The non-passivated ZnO showed a strong OH bonding signal. The formed HO-Zn-OH compound via moisture absorption will break the Zn-O bonding in ZnO crystal to form dangling bonds and charged scattering centers to lower the mobility strongly. In contrast to other passivation methods [14][15][16][17][18][19][20][21] , the LaO-based dielectric has important advantage of moisture absorption to lower the OH bonding formation as evident from the XPS data [25][26][27][28][29] . The remarkably high μ FE HfLaO/ZnO TFT suggests the excellent opportunity for both flexible and rigid display applications.
higher κ TiO 2 dielectric. The TiO 2 has higher κ value for low voltage operation. To improve the interface 30 , extra SiO 2 dielectric was inserted between ZnO and TiO 2 . To improve the leakage current via the low conduction band offset (ΔE C ) of TiO 2 , stacked TiO 2 /HfO 2 were applied 31 . Figure 2(a-c) show the transistor's drain-source current versus drain-source voltage (I DS -V DS ) and I DS versus gate-source voltage (I DS -V GS ) characteristics of ZnO/high-κ/metal-gate TFTs with and without HfLaO passivation. The ZnO TFTs without passivation show reasonable performance of I ON /I OFF of 2 × 10 5 , SS of 112 mV/dec, and a V T of 0.78 V. Here the gate leakage current is lower than I OFF due to the thick stacked gate dielectric. The ZnO TFTs after HfLaO passivation shows more than one order of magnitude higher I ON and 4 times lower I OFF , with large I ON /I OFF of 7 × 10 6 , small SS of 103 mV/dec, and a low V T of 0.13 V. These good device integrities were achieved at a low V D of 2 V that is crucial to lower the switching power by orders of magnitude than existing TFT devices. Besides, the steep SS can also turn on the transistor faster for a lower voltage and power operation.
The μ EF -V GS characteristics is plotted in Fig. 3 from the measured I DS -V GS characteristics. For control non-passivated devices, an acceptable peak μ FE of 43 cm 2 /Vs is obtained for room-temperature-processed ZnO TFT. The TFT devices after HfLaO passivation has remarkably high μ FE of 345 cm 2 /Vs; this is the highest value for TFT on flexible substrate 1-7 and is even higher than the reported IGZO and ZnON TFTs fabricated on rigid substrate 22,23 . The much improved μ FE for HfLaO-passivated device is owing to the higher I ON and the lower I OFF . It is important to notice that the μ FE decreases monotonically with decreasing gate length 32, 33 : where R SD is the source/drain series resistance, μ FE is the apparent field-effect mobility and μ 0 is the true field effect mobility. At long gate length, the μ FE is approaching to μ 0 ; thus, the long 48 μm gate length device was used.
To understand the mechanism of such large mobility improvement, material and structure analysis were performed. Figure 4(a) shows the secondary ion mass spectrometry (SIMS) depth profile, where a ZnO channel, HfO 2 , TiO 2 , and thin SiO 2 gate dielectric stack were recognized. The device structure of Al contact, ZnO channel, high-κ gate dielectric stack, and TaN metal-gate were also observable from the cross-sectional transmission electron microscopy (TEM) image shown in Fig. 4(b). The ZnO active layer forms columnar nano-crystalline structure with a size of ~10-20 nm. The formed crystalline structure is further evidenced from the X-ray diffraction (XRD) spectra shown in Fig. 4(c). Highly oriented phases of XRD peaks were measured, even though the ZnO was deposited by sputtering at room temperature. The full-width at half-maximum (FWHM) of XRD spectra are comparable with the data of ZnO published in literature 34,35 , while the IGZO has an amorphous structure 36 . Figure 5(a,b) show the XPS spectra without and with HfLaO passivation, respectively. The atomic composition of nano-crystalline structure is identified to be Zn 2+ -O 2− , as measured from the XPS spectra. It is important to notice that significant amount of OH bonding signal was also measured for non-passivated device. The OH bonding in nano-crystalline ZnO was originated from the moisture absorption of ambient air, even though dry process steps were used to fabricate the devices. Similar strong moisture absorption is well known in IGZO to cause degradation.
The chemical reaction of ZnO and H 2 O is expressed as: 2 2 In addition to surface, the tiny H 2 O molecule can also react with grain boundaries through the thin 20-nm ZnO. Here the grain boundaries are highly reactive due to their high defect density. Once the Zn(OH) 2 was formed, it damaged the Zn-O bonded nano-crystal and created dangling bonds that further form charged states in the ZnO bandgap. The decreased XPS OH signal and related charged defects are also supported from the high positive charge density (ΔQ p ) of 2 × 10 12 cm −2 , which was obtained from the V T shift (ΔV T ) between HfLaO-passivated and non-passivated ZnO devices shown in Fig. 3(b), from the ΔQ p = C G × ΔV T . Such positive charges and dangling bonds also found in the interim SiO x region between SiO 2 and Si body, the origin of positive fixed oxide charges in SiO 2 /Si metal-oxide-semiconductor field-effect transistor (MOSFET) shown in text book. On the other hand, the OH bonding signal in XPS spectra of Fig. 5(b) is much lowered for HfLaO passivated ZnO device. It is well known the high-κ gate dielectric will absorb the moisture [25][26][27][28][29] , especially the La 2 O 3 , which in turn reduce the Zn(OH) 2 formation.
The high-density positive ΔQ p further causes Fermi-level closer to valance band, increases the ZnO depletion region, and lower the n-type ZnO conduction, as shown in the schematic diagrams of Fig. 6. The electron wave-function in a MOSFET typically distributes over 20 nm 30 ; therefore the high-density ΔQ p will also increase electron scattering rate and decrease mobility. However, the passivation does not affect the gate EOT, because the EOT of a TFT only counts the dielectric next to the gate. Because proper passivation blocks the reaction between H 2 O and ZnO, the OH bonding in HfLaO/ZnO is much reduced to lower ΔQ p and potential barriers at grain boundaries. This in succession leads to much higher mobility, because the ZnO has overlapped s-orbitals for conduction. Table 1 compares the device performance of various materials on flexible and rigid substrates. The mobility of HfLaO-passivated ZnO TFT is higher than the IGZO and ZnON TFTs on rigid substrate 22, 23 that is also the record highest value for TFTs on flexible substrate 1-7 . This is possible because the poly-crystalline material always has better material quality and higher mobility than amorphous structure, and the mobility improvement can be as large as ~100 times for poly-Si versus amorphous-Si TFTs. The very high mobility ZnO TFT with excellent SS, large I ON /I OFF and low V D are vital for both DC and AC power saving. The simple process and low material cost of nano-crystalline ZnO device should have strong impact on next generation display, as long as OH bonding related charge traps and grain boundary potential barriers are improved by proper passivation. The achieved high mobility on amorphous material is also the enabling technology for high-speed 3D brain-mimicking chip 24 .
In conclusion, very high mobility, excellent SS, large I ON /I OFF , low V D , and low power operation were achieved in ZnO TFT device that is crucial for display and 3D IC. The excellent device integrity is due to the novel passivation scheme with simple process.

Methods
The bottom-gate ZnO/high-κ/metal-gate TFTs were made on flexible polyethylene naphthalate (PEN) substrate. In addition to its low cost, the PEN substrate has good properties of a low linear thermal expansion coefficient, surface smoothness, and optical clarity. A 300-nm smoothing SiO 2 layer was first deposited on PEN substrate. Then the 60-nm TaN gate metal, tri-layer gate dielectrics of 50-nm HfO 2 , 40-nm TiO 2 and 4-nm-SiO 2 , and a 20-nm ZnO active layer were deposited by physical vapor deposition (PVD). Then the Al source/drain (S/D) electrodes was formed. Finally, the device was passivated by 20 nm thick HfLaO dielectric with opened S/D probing window. The TaN gate electrode was deposited by sputtering at a power of 800 W, Ar/N 2 of 100/10 sccm, and a pressure of 3 × 10 −3 torr. The gate dielectric stacks were deposited by electron-gun evaporation at 5 KV, and the deposition rates were 0.24/0.2/0.1 Å/sec, respectively. The ZnO channel were deposited by sputtering at a power of 100 W, Ar/O 2 of 20/5 sccm, and 1 Å/sec deposition rate. The Al source-drain was deposited by thermal evaporation deposition. The HfLaO was deposited by electron-gun evaporation at a deposition rate of 0.15 Å/sec. Before deposition, the chambers were pumped down to 3 × 10 −6 torr. The low deposition rate is important to reach good quality. No post-deposition annealing was used that is the merit of this work. The gate size of fabricated TFT is 48-μm × 505-μm. To investigate the large mobility improvement, X-ray diffraction (XRD), secondary ion mass spectrometry (SIMS), cross-sectional transmission electron microscopy (TEM), and X-ray photoelectron spectroscopy (XPS) were used to analyze the material property. Very low etching rate of 0.2 Å/sec was used in the XPS measurement due to the thin 20 nm HfLaO passivation layer.