Main

For quantum computers to solve problems in materials design, quantum chemistry and cryptography, in which known speed-ups relative to classical computations are attainable, currently proposed algorithms require trillions of qubit gate operations to be applied in an error-free manner1,2. Despite impressive progress over the past few decades in reducing qubit error rates at the physical hardware level, the state-of-the-art remains about nine orders of magnitude away from these requirements. A path towards closing the error-rate gap is through quantum error correction (QEC)3,4,5, which can exponentially suppress errors through the redundant encoding of information across many noisy physical qubits.

Recently, QEC experiments have been performed in various hardware platforms, including superconducting quantum circuits25,26,27,28, trapped ions29 and neutral atoms30. Some of these experiments are approaching26, or have surpassed28, the threshold at which scaling of the error-correcting code size leads to exponential improvements in the logical qubit error rate. In these experiments, the qubits are realized using a simple encoding into two levels of a physical element, leaving them susceptible to environmental noise that can cause both bit and phase-flip errors. Correcting for both types of error requires QEC codes such as the surface code25,26,27, which have a relatively high overhead penalty1.

Alternatively, we can use a layered approach to noise protection by starting from an encoded qubit that natively suppresses errors. An example is bosonic qubits, in which qubit states are encoded in the infinite-dimensional Hilbert space of a bosonic mode (a quantum harmonic oscillator) using bosonic QEC6,31,32. In bosonic QEC, the large oscillator Hilbert space is exploited to suppress errors. Experiments demonstrating this exploitation at the single bosonic mode level have been performed using cat codes21,22,23,33,34,35, binominal codes36 and GKP codes37,38,39. At the same time, various proposals have been put forward to further scale bosonic QEC by concatenating it with an outer code across multiple bosonic modes6,8,9,10,11,12,13,14,15,16,18,40, leveraging the protection offered in each bosonic mode to reduce the overall resource overhead for QEC.

In this work, we demonstrate a scalable, hardware-efficient logical qubit memory built from a linear array of bosonic modes using a variant of the repetition cat code proposal in ref. 10. In particular, we stabilize noise-biased cat qubits in individual bosonic modes. Bit-flip errors of the cat qubits are natively suppressed at the physical level, and the remaining phase-flip errors are corrected by an outer repetition code. The use of a repetition code enables low overhead because of its large error rate threshold and linear scaling of code distance with physical qubit number10,12,15. In what follows, we describe a microfabricated superconducting quantum circuit that realizes a distance d = 5 repetition cat code logical qubit memory, present a noise-biased CX gate for implementing error syndrome measurements with ancilla transmons and study the logical qubit error correction performance.

Quantum device realizing a distance-5 repetition code

A schematic of our repetition code device and the corresponding superconducting circuit layout are shown in Fig. 1. The distance d = 5 repetition code consists of five bosonic modes that host the data qubits (blue), along with four ancilla qubits (orange). The bosonic modes, also referred to as storage modes, are coplanar waveguide resonators with an average T1 time of more than 60 μs and an average T2 time of more than 80 μs. The ancilla qubits are fixed-frequency transmons and are coupled to the storage modes by tunable-transmon couplers41,42 that realize a tunable dispersive coupling (see ref. 24 and Supplementary Information). This dispersive interaction is used for a controlled-X operation (CX gate), with the ancilla transmon as the control and the data qubit as the target. Using the CX gates, we measure the repetition code stabilizers \({\widehat{X}}_{i}{\widehat{X}}_{i+1}\) (grey triangles), equivalent to measuring the joint photon-number parity of two neighbouring storage modes. Each ancilla qubit can be read out and reset through a readout resonator43,44.

Fig. 1: Repetition code of bosonic qubits.
figure 1

a, Schematic of the repetition code device. Data qubits S1, …, S5 (blue) are encoded into the Hilbert space of a quantum harmonic oscillator. Each cat qubit is stabilized by a buffer mode B1, …, B5 (green). The ancilla qubits A1, …, A4 (orange) are transmon qubits that detect Z errors (see example with red arrows) on the data qubits by measuring repetition-code stabilizers. b, Circuit layout of the repetition code device using a flip-chip architecture (Supplementary Information). The five bosonic modes (Si) are coplanar waveguide resonators. Each resonator is connected to a buffer mode (Bi). Buffer modes are damped through a multi-pole filter. Ancilla transmons (Ai) are connected to the storage modes by tunable couplers (Ci,j). Scale bar, 1 mm. c,d, Magnified circuit sections showing a storage-buffer subsystem (c) and an ancilla transmon coupled to its neighbouring storage modes by tunable couplers (d). e, Cat qubit encoding in a bosonic mode with experimentally measured Wigner functions of the four basis states of a cat qubit and arrows representing X and Z errors. f, Bit-flip and phase-flip times of the five cat qubits in our device under simultaneous two-photon dissipation. Error bars (standard error) incorporate sampling and fit error.

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Each data qubit in our system is a cat qubit encoded in storage mode20,21,22. The basis states of a cat qubit are shown in Fig. 1e along with their experimental Wigner tomograms45. The |0⟩ and |1⟩ computational basis states are approximately the |α⟩ and |−α⟩ coherent states, respectively, with a mean photon number of ∣α∣2. The complementary basis states are exactly the even and odd cat states |±⟩ ∝ |α⟩ ± |−α⟩. Thus, a bit-flip (X) error is a 180° rotation in the phase space mapping |α⟩ ↔ |−α⟩, and a phase-flip (Z) error corresponds to a parity flip between the even and odd cat states. Owing to the phase-space separation of the |±α⟩ coherent states, bit-flip error rates can be exponentially suppressed with cat size ∣α∣2 (refs. 23,24,34,35). By contrast, phase-flip errors, which are caused by single-photon loss and heating, have a rate that increases linearly with ∣α∣2.

To ensure that their noise bias is maintained over time, the cats are stabilized using two-photon dissipation, confining them to the |±α⟩ manifold20,21,22. To realize the two-photon dissipation, we nonlinearly couple each storage mode to a lossy buffer mode (green), which is implemented using a version of the asymmetrically threaded SQUID element23,24. Our buffer mode implementation ensures that the storage-mode lifetime and linearity are not degraded by the coupling to the lossy and nonlinear buffer (see ref. 24 and Supplementary Information).

Figure 1f shows the bit-flip and phase-flip times of all five data cat qubits when they are being simultaneously stabilized by two-photon dissipation. Over the range of ∣α∣2 considered, the bit-flip times of our cat qubits increase exponentially with the mean photon number ∣α∣2. As expected, the phase-flip times degrade as T1,eff/∣α∣2, where the effective storage lifetimes under two-photon dissipation, T1,eff, are in the range 57–68 μs. A particularly important feature of our cat qubits is that a large noise bias is achieved even with small values of ∣α∣2. Concretely, at ∣α∣2 = 2, we achieve greater than 1 ms bit-flip times and 27–33 μs phase-flip times. This constitutes a sizable (>30) noise bias and at the same time a long phase-flip time in comparison to an error correction cycle time (2–3 μs).

Noise-biased CX gates in the repetition cat code

Syndrome measurements require a CX gate between a data cat qubit and an ancilla qubit with computational states |0a⟩ and |1a⟩. This requires us to realize a noise-biased CX gate that minimizes undesired bit flips on the target cat qubit caused by ancilla errors. Although cat qubits can be used as ancilla qubits to implement noise-biased CX gates, these gates can induce substantial control errors and require a complex drive scheme10,11,15.

To avoid this issue, we use transmons as ancilla qubits whose lowest three energy eigenstates are denoted by |g⟩, |e⟩ and |f⟩. We realize the CX gate with a storage-ancilla dispersive coupling in which the data cat qubit rotates by 180° conditional on the ancilla being in |1a⟩ (refs. 46,47,48). As in refs. 49,50,51, we encode the ancilla qubit into the states |0a⟩ = |g⟩ and |1a⟩ = |f⟩ and engineer an approximately χ-matched dispersive interaction between the ancilla and the storage mode. The χ-matching means the storage frequency shift is similar for the ancilla in |e⟩ and |f⟩ and thus the noise bias of a CX gate is robust against the dominant ancilla decay events. Only subleading ancilla error mechanisms such as two sequential decay events and heating will cause bit-flip errors on the data cat qubit. In our implementation, the dispersive interaction is tunable, the χ-matching is natively realized without drives, and dissipative protection allows for robustness to inexact χ-matching (Supplementary Information).

Figure 2a shows a control sequence involving a CX gate similar to that used for an error correction syndrome measurement. We illustrate the robustness of our CX gate to ancilla decay by measuring the action of the gate on initial state \(| \alpha \rangle \otimes | g,e,{\rm{or}}\,f\rangle \) of the storage mode and ancilla. Before the CX gate begins, we turn off the cat qubit stabilization to allow the storage mode to rotate freely. Then we activate the CX gate by applying a flux pulse on the tunable coupler. As shown by the Wigner tomograms, the storage mode does not rotate when the ancilla is in |g⟩, whereas it rotates by approximately 180° over the course of a CX gate when the ancilla is in |e⟩ or |f⟩. Owing to the imperfect χ-matching, the storage mode has slightly overrotated when the ancilla is in |e⟩. Moreover, miscalibrations, self-Kerr nonlinearities and decoherence can cause mis-rotations and distortion of the storage-mode states. Notably, all these imperfections can be corrected with high probability when the two-photon dissipation is turned back on after the CX gate, as shown in the last column of the Wigner tomograms. To further highlight the importance of applying the two-photon dissipation, Fig. 2b shows the results of 10 repetitions of the CX gate cycle with and without the pulsed cat qubit stabilization. Without stabilization, errors accumulate over multiple rounds causing large distortion in the final storage mode state. With stabilization applied in every cycle, the storage mode stays well confined to the ideal target coherent state.

Fig. 2: Noise-biased CX gate between a transmon and a cat qubit.
figure 2

a, CX gate sequence. At the start of the sequence, the ancilla is initialized and cat qubit stabilization (blue arrows) is on. The stabilization is then turned off and the CX gate is applied between the ancilla and cat qubit. After the CX gate, the stabilization is turned back on and the ancilla qubit is read out and reset to |g⟩. Through the experimentally measured Wigner functions, we show the evolution of the storage state during the sequence for each of the ancilla states |g⟩, |e⟩ and |f⟩, with an initial storage-mode state |α⟩. b, Storage-mode Wigner tomograms before and after 10 applications of the CX gate sequence with the ancilla in |g⟩ and storage initialized in |α⟩. The sequence is applied with and without stabilization. c, Characterization of the CX gate. We apply repeated CX2 cycles (see main text) with a cycle duration of 3 μs and plot the measured bit-flip time of the cat qubit as a function of cat qubit photon number, ∣α∣2, for different ancilla states. The inset shows the measured phase-flip times (points) and a fit (line) when the ancilla is initialized to |g⟩ + |f⟩. Error bars (standard error) incorporate sampling and fit errors. a and b use the same colour bar.

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We quantify the performance of our CX gate by repeatedly applying the pulse sequence of Fig. 2a except with the single CX replaced by a single pulse that is the equivalent of two CX gates (a CX2 gate) (Supplementary Information). This ensures that, similar to a stabilizer measurement, cat bit-flip times are first-order insensitive to ancilla state preparation errors.

Figure 2c shows bit-flip times measured during repeated CX2 cycles for a representative interaction between ancilla A1 and storage S1. Each cycle has a length of 3 μs. We measure the bit-flip times with the ancilla in state |g⟩ + |f⟩, as would be used for syndrome extraction, and control experiments with the ancilla in |g⟩ and |g⟩ + |e⟩. The black curve is a reference showing the bit-flip times in the case for which the two-photon dissipation is continually applied (as in Fig. 1d). When the gates are applied with the ancilla in |g⟩, bit-flip times exceeding 5 ms are achieved. The degradation relative to the reference performance at ∣α∣2 ≳ 3 is because of ancilla or coupler heating during the CX2 gate. With the ancilla in |g⟩ + |e⟩, bit-flip times are severely limited to well under 1 ms because of the storage dephasing caused by the |e⟩ → |g⟩ decay errors of the ancilla. With the initial ancilla state |g⟩ + |f⟩, we recover bit-flip times over 1 ms at ∣α∣2 ≥ 3 because of the insensitivity to the |f⟩ → |e⟩ decay events of the ancilla afforded by χ-matching (here χge/χgf ≈ 1.1; Supplementary Information). The remaining ancilla-induced errors are from higher-order mechanisms such as double decay. In Fig. 2c (inset), we also show the corresponding phase-flip times with the ancilla in the state |g⟩ + |f⟩. An effective storage lifetime T1,eff of 63 ± 2 μs is inferred, showing no substantial difference from T1,eff = 68 ± 2 μs measured in Fig. 1 in the absence of CX2 gate application. The corresponding bit- and phase-flip errors per cycle are (3.5 ± 0.4) × 10−3 and (9.6 ± 0.4) × 10−2, respectively, at ∣α∣2 = 2, corresponding to a noise bias greater than 25.

Correcting phase-flip errors with the repetition code

Equipped with the noise-biased CX gates, we now demonstrate the ability to correct the dominant phase-flip errors using a repetition code. Phase-flip errors are detected by repeatedly measuring the stabilizer generators of the repetition code, \({\widehat{X}}_{i}{\widehat{X}}_{i+1}\) (for i = 1, …, d − 1). As shown in Fig. 3a, each measurement of a stabilizer generator, referred to as a syndrome measurement, comprises initialization of the ancilla Ai, two CX gates between Ai and its adjacent data qubits Si and Si+1, and finally measurement and reset of the ancilla. During the measurement and reset, we turn on the dissipative stabilization on all the cat qubits. Each syndrome measurement cycle has a conservatively chosen duration of 2.8 μs (Supplementary Information).

Fig. 3: Detecting and correcting phase-flip errors with the repetition code.
figure 3

a, Error correction circuit, showing repeated error correction cycles with a duration of 2.8 μs. b, Detection probabilities for the measured stabilizers versus error correction cycle for three different cat qubit photon numbers, ∣α∣2 = 1, 2 and 3. Bold traces correspond to the average over the individual stabilizer traces. Error bars represent the standard error of the mean. c, Depiction of erasures occurring in the repetition code experiment due to ancilla decay from |f⟩ to |e⟩. We show shots of the experiment from a representative stabilizer, in which |f⟩ is light grey, |g⟩ is dark grey and the erasure state |e⟩ is shown in red. d, Effective syndrome measurement error extracted from the QEC graph before and after accounting for the erasure for ∣α∣2 = 1. Bold traces correspond to averaging over the stabilizers. e, Example fits of the decay of the X logical operator for the distance-5 repetition code for different photon numbers. f, Error corrected logical phase-flip probability per cycle (ϵL,phase-flip) and logical X lifetime (TX) as a function of ∣α∣2 for the different repetition code sections. Data and fits are shown with (squares and solid curves) and without (circles and dashed curves) inclusion of erasure information. The fits are to the power law (|α|2)γ for ∣α∣2 ≥ 1.5. Faded points indicate fits binned by the number of even cat states |+⟩ in the initial state and serve to indicate the spread from asymmetric error rates at low photon numbers (Supplementary Information). The dotted purple curve shows the simulated logical phase-flip probability for the distance-5 section. Error bars (standard error) incorporate sampling and fit errors.

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After running an experiment with many error correction cycles, we decode the syndrome measurements using minimum-weight perfect matching (MWPM)52,53. As the first step in this decoding process, we compare the outcomes of consecutive syndrome measurements. Consecutive measurement outcomes that differ indicate an error and are referred to as detection events54.

In Fig. 3b, we plot the probability of detection events over time for each ancilla and for different values of ∣α∣2. These probabilities increase with ∣α∣2, reflecting that the phase-flip error rates of the cat qubits scale with photon number. Notably, the detection probabilities in our system are approximately constant over time. We attribute the constant detection probabilities here to the dissipative stabilization of the cat qubits, which prevents the accumulation of leakage out of the cat qubit subspace without requiring additional protocols for active leakage suppression55,56.

Further improvements in error decoding can be achieved by making use of the fact that |f⟩ → |e⟩ ancilla transmon decay errors constitute detectable erasure errors57,58 as shown in Fig. 3c. Specifically, although the χ-matching ensures that decay to |e⟩ is unlikely to cause a bit-flip error, the decay has a high probability (about 50%) to cause a syndrome measurement error. We detect these erasures using a three-state transmon readout that separately resolves |g⟩, |e⟩ and |f⟩. The heatmap shows the occurrence of erasure events (indicated in red) interspersed among valid syndromes in the data (grey shades). We account for these erasures in decoding by only using the non-erased syndromes (Supplementary Information). As shown in Fig. 3d, doing so effectively reduces the syndrome measurement error probability by over a factor of two for ∣α∣2 = 1.

We characterize the ability of the repetition code to correct cat qubit phase-flip errors by measuring the decay time of the repetition code logical operator \({\widehat{X}}_{{\rm{L}}}={\widehat{X}}_{1}\). We prepare the repetition code into a randomly chosen one of the 2d possible product cat states (for example, |+⟩|−⟩|−⟩|+⟩|+⟩), perform a variable number of QEC cycles, and finally measure the parity of each storage-mode state (Supplementary Information). Corrections from the MWPM decoding are applied in the software. We fit \(\langle {\widehat{X}}_{{\rm{L}}}(t=0){\widehat{X}}_{{\rm{L}}}(t=t)\rangle \) to a decaying exponential and define the decay time constant, TX, as the logical X lifetime (Fig. 3e). From TX, we compute the logical phase-flip error per cycle as ϵL,phase-flip = Tcycle/(2TX).

We can study the performance of the error-correcting code in situ because we can tune the data qubit phase-flip error rate by varying ∣α∣2. In Fig. 3f, we plot the measured ϵL,phase-flip versus ∣α∣2 for the distance-5 repetition code and the two minimally overlapping distance-3 repetition codes contained within it. As expected, as the photon number increases, the logical error probability increases because the cat qubit phase-flip rates increase. Across the measured range of ∣α∣2, we find that the distance-5 code outperforms the distance-3 subsections. This indicates that the physical phase-flip error rates of our system are below the error threshold of the repetition code for this range of ∣α∣2. Note also that there is a sizable reduction in the logical phase-flip rate when the erasure information is incorporated (for example, by about 20% at ∣α∣2 = 1.5 for d = 5), a result of the reduced effective measurement error probabilities.

More quantitatively, the logical phase-flip rate is expected to scale as (|α|2)γ (refs. 53,59), where ∣α∣2 is a proxy for the cat qubit phase-flip error rate. When the erasure information is incorporated, we estimate from fits to the measured logical phase-flip probability versus ∣α∣2, scaling exponents of γ = 1.63 ± 0.04 and γ = 1.86 ± 0.03 in the two d = 3 subsections, and γ = 2.31 ± 0.02 in the full d = 5 section. The increase in scaling exponent from d = 3 to d = 5 shows that the increased code distance is providing greater resiliency to phase-flip errors. Although the measured values of γ are lower than the ideal values, γ = (d + 1)/2, they are consistent with simulations (shown in Fig. 3f as a dotted purple curve for the distance-5 code) based on a simple model that incorporates the measured probabilities of cat phase flips, ancilla erasures and syndrome measurement error.

Maintaining long bit-flip times in a repetition cat code

Having demonstrated the ability to correct the dominant phase-flip errors of cat qubits using a repetition code, we now characterize the logical bit-flip rates. Unlike the logical phase flips that are corrected using the repetition code syndrome measurements, logical bit flips are passively suppressed at the level of the individual cat qubit encodings. As a result, achieving long logical bit-flip times is challenging because any single cat qubit bit-flip event in any part of the repetition code directly causes a logical bit-flip error. We now demonstrate that because of detailed design and calibration strategies (Supplementary Information), we can maintain long logical bit-flip times during the syndrome extraction of the repetition code in our device.

We characterize the logical bit-flip probabilities by measuring the decay time, TZ, of the logical Z operator \({\widehat{Z}}_{{\rm{L}}}={\widehat{Z}}_{1}{\widehat{Z}}_{2}\cdots {\widehat{Z}}_{d}\). To do so, we first initialize the data cat qubits in a tensor-product of coherent states (for example, \({| \alpha \rangle }^{\otimes d}\)), apply a variable number of syndrome extraction cycles and finally perform single-shot cat qubit Z-basis measurements (Supplementary Information) to measure \({\widehat{Z}}_{{\rm{L}}}\). The logical Z lifetime, TZ, is then obtained by fitting the decay curve of \(\langle {\widehat{Z}}_{{\rm{L}}}(t=0){\widehat{Z}}_{{\rm{L}}}(t=t)\rangle \) to an exponential (Fig. 4a). From TZ, we compute the logical bit-flip error per cycle as ϵL,bit-flip = Tcycle/(2TZ).

Fig. 4: Characterizing logical bit-flip error rates.
figure 4

a, Fitted decay curve of the logical Z operator for several storage mean photon numbers for the distance-5 code. Error bars capture sampling error. b, Logical bit-flip probability per cycle (ϵL,bit-flip) and logical Z lifetime (TZ) as a function of ∣α∣2 for the two distance-3 repetition-code sections and the distance-5 section. Solid lines correspond to data and dotted lines correspond to a phenomenological model. Error bars (standard error), capturing sampling variance and fit uncertainty, are smaller than the markers.

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Figure 4b shows ϵL,bit−flip as a function of ∣α∣2 for the distance-5 (purple) and two distance-3 (red and blue) sections. At a low ∣α∣2 of 1, ϵL,bit-flip is about 2% for the two distance-3 sections and around 4% for the distance-5 section. As ∣α∣2 increases to 4, ϵL,bit-flip drops to below 0.5% for the two distance-3 sections and below 1% for the distance-5 section, because of the increased level of bit-flip protection from the cat qubits. As ϵL,bit-flip combines the bit-flip error contributions from all the cat qubits and CX gates, the distance-5 section, with more bit-flip error locations, has higher ϵL,bit-flip. Nevertheless, the large noise bias maintained throughout the error correction cycle enables us to achieve sub-1% logical bit-flip probability even for the distance-5 section, which involves 5 cat qubits and 8 CX gates.

Figure 4b shows a phenomenological model of the logical bit-flip errors based on independent CX and cat qubit characterization experiments. The agreement between the model and measurements indicates that there is no marked degradation in cat qubit bit-flip rates when integrated together into the repetition code.

Overall memory lifetime and error budget

Combining the logical bit-flip and phase-flip probabilities, we show in Fig. 5a the overall logical error per cycle25,26, ϵL = (ϵL,phase-flip + ϵL,bit-flip)/2 ((PX + 2PY + PZ)/2 under Pauli noise), for the repetition cat codes. As ϵL,phase−flip increases with ∣α∣2, while ϵL,bit-flip decreases with ∣α∣2, ϵL is minimized at a certain value of ∣α∣2. The shorter distance-3 codes favour operation at smaller ∣α∣2 because of their weaker protection against phase-flip errors. By contrast, the distance-5 code has better protection from phase-flip errors and can thus operate at higher ∣α∣2, benefiting from the larger noise bias of the cat qubits there. The best-measured performance for the distance-5 section is ϵL = 1.65 ± 0.03% at ∣α∣2 = 1.5. This is comparable to the best observed performance for the distance-3 sections which are ϵL = 1.83 ± 0.03% and ϵL = 1.67 ± 0.04% at ∣α∣2 = 1 (average ϵL = 1.75 ± 0.02%).

Fig. 5: Logical qubit memory performance.
figure 5

a, Overall logical error per cycle of the repetition cat code, ϵL = (ϵL,bit-flip + ϵL,phase-flip)/2, versus cat qubit mean photon number ∣α∣2. As in Fig. 3f, the faded points correspond to fits to groupings of the data by the number of even cat states in the initial state. The lines are guides to the eye, computed by interpolating both the logical phase-flip and bit-flip probabilities, ϵL,phase-flip and ϵL,bit-flip, respectively. b, Error budget for the distance-5 repetition code using erasure information. Different shades of colour correspond to the different per cat (or per CX gate) contribution to the error budget. Error bars (standard error) incorporate sampling and fit errors.

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We emphasize that a repetition code of biased noise qubits does not possess a proper asymptotic threshold because physical bit-flip errors are uncorrectable and place a lower bound on the achievable logical error12. Still, at large enough noise bias, the logical error can be reduced by increasing code distance before encountering this limit. By contrast, without bias, overall logical error would inevitably increase with code distance. The large noise bias in our device is apparent from the observations that we achieve comparable logical error as we increase distance and that the distance-5 section outperforms the distance-3 sections for ∣α∣2 ≥ 1.5.

In Fig. 5b, we use models of the logical bit-flip and phase-flip errors to construct an error budget for the distance-5 repetition cat code (Supplementary Information). The error budget is broken into four error mechanisms: cat intrinsic bit-flip errors (red), CX-gate-induced bit-flip errors (blue), cat intrinsic phase-flip errors capturing idling and CX gate phase flips (green) and syndrome measurement errors (grey). The bit-flip mechanisms (first two) dominate at small ∣α∣2, and the phase-flip (latter two) mechanisms dominate at large ∣α∣2. The minimum logical error rate is achieved at ∣α∣2 ≃ 1.5, for which the bit-flip and phase-flip contributions are comparable. Notably, at this optimal value of ∣α∣2 ≃ 1.5, the cat intrinsic errors are the dominant contributors as opposed to additional CX-gate-induced errors.

Conclusion and outlook

In this work, we have performed error correction using a concatenated bosonic code, in which bit-flip errors are suppressed with a bosonic cat code and residual phase-flip errors are corrected with a repetition code. This experiment serves as a promising first step in taking advantage of bosonic qubits, and also noise bias, to improve the hardware efficiency of QEC. Furthermore, having constructed our logical qubit memory using planar microfabrication processes, this work highlights the potential scalability of the concatenated bosonic qubit architecture.

The logical error in our current device is dominated by intrinsic cat bit-flip and phase-flip errors (Fig. 5b), but there are several strategies to reduce these errors in the near term. We project that by optimizing cycle time and using the further optimized cat qubit circuit in ref. 24, an overall logical error per cycle approaching 0.5% (limited by transmon errors) is achievable with a distance-5 code even without improvements in the component coherence times.

The use of ancillary transmons for syndrome measurements is important to our experiment, enabling noise-biased CX gates without undesired control errors, but comes along with ancilla-induced bit-flip errors. The logical performance at present is not limited by these errors, and improved ancilla lifetimes of 1 ms would ideally lower their probability to about 10−6 per CX (Supplementary Information). However, in the long term, it will be necessary to eventually correct ancilla-induced bit flips, which can be accomplished by concatenating cat qubits into surface codes tailored to noise-biased qubits14,15. We analyse this approach in ref. 60 and find that marked hardware-efficiency improvements are possible relative to the case without biased noise.

An alternative approach to overcome the transmon-induced limitations is to use cat qubits as the ancillas. This was proposed in ref. 10, but existing proposals for cat–cat CX gates are hampered by large control errors10,12,15. Searching for ways to implement syndrome measurements with a large noise bias but without undesired control errors61,62,63 thus represents an important direction for future research. If the performance of gates were limited only by the intrinsic bit-flip and phase-flip rates of the cats, sizable reductions in logical-memory overhead would be possible with realistic device parameters. For example, with the cat qubit bit-flip times, we show in ref. 24 and improved storage lifetimes of about 300 μs (ref. 64), we project (Supplementary Information) that ϵL ~ 10−5 could be achieved with a d = 11 repetition cat code. Furthermore, with ≳100 s bit-flip times34, and ms-scale storage T1 (ref. 65), algorithmically-relevant ϵL ~ 10−8 could be achieved with similar overhead. Although these examples assuming coherence-limited gates are idealized hypotheticals, they nevertheless highlight the potential of cat qubits to enable hardware-efficient logical qubits.