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Heterogeneous integration of spin–photon interfaces with a CMOS platform

Abstract

Colour centres in diamond have emerged as a leading solid-state platform for advancing quantum technologies, satisfying the DiVincenzo criteria1 and recently achieving quantum advantage in secret key distribution2. Blueprint studies3,4,5 indicate that general-purpose quantum computing using local quantum communication networks will require millions of physical qubits to encode thousands of logical qubits, presenting an open scalability challenge. Here we introduce a modular quantum system-on-chip (QSoC) architecture that integrates thousands of individually addressable tin-vacancy spin qubits in two-dimensional arrays of quantum microchiplets into an application-specific integrated circuit designed for cryogenic control. We demonstrate crucial fabrication steps and architectural subcomponents, including QSoC transfer by means of a ‘lock-and-release’ method for large-scale heterogeneous integration, high-throughput spin-qubit calibration and spectral tuning, and efficient spin state preparation and measurement. This QSoC architecture supports full connectivity for quantum memory arrays by spectral tuning across spin–photon frequency channels. Design studies building on these measurements indicate further scaling potential by means of increased qubit density, larger QSoC active regions and optical networking across QSoC modules.

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Fig. 1: Comprehensive architectural design.
Fig. 2: QSoC fabrication.
Fig. 3: QSoC characterization.
Fig. 4: Quantum emitter spectral tuning and spin state preparation and measurement.
Fig. 5: QSoC enables large-scale fully connected qubit graph with further scaling.

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Data availability

The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request. The data that support the findings of this study are also openly available at https://doi.org/10.6084/m9.figshare.25374583.v1 (ref. 61).

Code availability

Our code and model checkpoint are available at https://doi.org/10.6084/m9.figshare.25374610.v1 (ref. 55).

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Acknowledgements

This work was supported by the MITRE Corporation Quantum Moonshot Program, the National Science Foundation (NSF) STC Center for Integrated Quantum Materials (grant no. DMR-1231319), the ARO MURI W911NF2110325 and the NSF Engineering Research Center for Quantum Networks (grant no. EEC-1941583). L.L. acknowledges funding from NSF QISE-NET Award (grant no. DMR-1747426). L.D. and C.E.-H. acknowledge funding from the European Union’s Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie grant agreement nos. 840393 and 896401. I.H. acknowledges the funding support by the NSF RAISE-TAQS (grant no. 1839159). K.C.C. acknowledges funding support by the NSF Graduate Fellowship. M.E.T acknowledges support from the ARL ENIAC Distinguished Postdoctoral Fellowship. H.C. acknowledges the Claude E. Shannon Fellowship. M. I. I. and R. H. acknowledge funding support by the NSF RAISE-TAQS (grant no. 1839159) and MIT MTL Center of Integrated Circuits and Systems. We thank A. Menssen for the discussion of the SLM application. We thank R. Chen for help with the foundry tape out and E. Bersin for useful comments on the manuscript. L.L. thanks S. Wang for the kind support.

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Authors and Affiliations

Authors

Contributions

L.L. conducted device design and fabrication, large-scale heterogeneous integration and measurements of the whole experiment. L.D.S. contributed to the cryogenic measurement setup and the experiment automation code. I.H. performed the tape out of the CMOS chip and contributed to the room-temperature measurement setup. K.C.C. contributed to the diamond fabrication and cryogenic measurement. Y.S., I.C., M.T., Y.H. and Y.G. contributed to the setup of the cryogenic experiment. H.C. contributed to the theoretical analysis of the architecture, C.E.-H. contributed to the transfer print stage for the transfer process, J.D. contributed to the transfer and the scientific plotting. Y.G. performed the COMSOL simulation for the strain tuning. G.C. contributed to characterizing the linewidth of the colour centre to verify the colour centre annealing properties. M.I.I. and R.H. provided an experience for the CMOS tape out. D.E. conceived the QSoC architecture and the frequency-shifted qubit graph algorithms and supervised the whole project. G.G. contributed to quantum algorithms. D.E. and L.L. designed the experiment. L.L. wrote the manuscript with input from all authors.

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Correspondence to Linsen Li or Dirk Englund.

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Extended data figures and tables

Extended Data Fig. 1 CMOS post-processing procedure.

a, Optical microscope image of a 3 mm × 3 mm bare die CMOS chip from the foundry, with alignment markers for the following process (scale bar 500 μm). b, Optical microscope image after the first photolithography (scale bar 500 μm), created the initial photoresist layer defining the locking structure of the chiplet. c, Optical microscope image after the first dry etching (scale bar 100 μm). d, Optical microscope image after wet etching (scale bar 100 μm), resulting in the QMC oxide locking structure. e, Optical microscope image after second photolithography and dry etching (scale bar 500 μm), formed the QMC platform region for QMC placement. f, Optical microscope image after third photolithography (scale bar 500 μm), prepared the chip for subsequent etching to expose the internal routing metal layer for the wire bonding region. g, Cross-section of the post-processed CMOS chip, with M3-M5 corresponding to metal layers 3 to 5 in the foundry metal definition; this CMOS process has a total of 6 metal layers.

Extended Data Fig. 2 CMOS post-processing result.

a, Optical microscope image of a single post-processed CMOS socket unit (scale bar 10 μm). b, Optical microscope image of an 8 × 8 array of post-processed CMOS sockets (scale bar 100 μm). c, Optical microscope image of the central region of the post-processed CMOS chip (scale bar 100 μm). d, SEM image of the post-processed CMOS socket unit (scale bar 100 μm). e, Optical microscope image of a 3 mm × 3 mm bare die CMOS chip from the foundry (scale bar 500 μm). Central red region is the target diamond integration region. f, The magnetic field distribution in the QSoC central region (red rectangle region in e, where the diamond QMCs locate in (scale bar 50 μm). g, The magnetic field distribution of the pink rectangle in f, which shows the microwave field of the CMOS backplane (scale bar 20 μm).

Extended Data Fig. 3 Detailed of lock-and-release transfer operation for QSoC fabrication.

a, Setup for the large-scale heterogeneous integration process between the fabricated parent diamond substrate and the target CMOS chip. The parent diamond was placed on a cut polydimethylsiloxane (PDMS) gel attached to a glass slide. The CMOS chip was mounted on a motorized stage with controllable horizontal (x) and lateral movement (y) as well as rotation (ψ). The diamond-attached glass was screwed to a 3-axis motorized stage with 3-axis piezo control along with the pitch and roll angle control knobs to align the surface of the diamond parallel to the CMOS chip surface. The chiplet alignment can be viewed through a microscope with variable magnification and a long working distance objective. b, Cross-section of the unit QMC and its corresponding CMOS locking structure during the transfer process.

Extended Data Fig. 4 Diamond QMC array fabrication and gas tuning process for dielectric antenna resonant wavelength adjusting.

a, Dark-field optical microscope image of the QMC array on the parent diamond (scale bar 100 μm). b, Optical microscope image of a single QMC with 16 quantum channels. (scale bar 10 μm). c, Redshift of the cavity resonance due to gas deposition on the cavity, A larger PL number indicates a later measurement time during the gas deposition process. d, Blue-shift of the cavity resonance resulting from gas desorption using a pulsed high-power laser.

Extended Data Fig. 5 The Purcell enhancement of the resonant dielectric antenna.

a, Simulated Purcell factor and far-field distribution of the quantum emitter in the center of the optimized resonant dielectric antenna. b, Resonant dielectric antenna spectrum (interference between laser reflection and resonant dielectric antenna reflection) displaying off-resonant (black) and on-resonant (red) peaks with the SnV ZPL wavelength. The inset shows the simulated electric field distribution (depicting the real part of the electric field, with red being positive and blue being negative) overlaid with the edge of the resonant dielectric antenna design, assuming that the dipole is at the center of the resonant dielectric antenna with an in-plane orientation perpendicular to the nanobeam. Four pairs of half-round bumps are placed on each side of the cavity. The centers of the four bumps are 200 nm, 600 nm, 1,070 nm, and 1,470 nm from the cavity center, and their radii are 50 nm, 50 nm, 50 nm, and 80 nm, respectively. c, Representative lifetime measurements when the resonant dielectric antenna is on/off-resonant with the SnV ZPL after/before gas tuning are shown in red/black, respectively. The lifetime of another SnV in the bulk diamond is shown in magenta. The fitted results for these lifetimes are the bulk material τbulk = 4.12 ns, the emitter in the off-resonance dielectric antenna τoff = 5.56 ns, and τon = 2.32 ns after tuning the dielectric antenna on-resonance with its ZPL.

Extended Data Fig. 6 Diamond quantum emitter widefield PLE cumulative distribution function statistics.

a, The cumulative distribution function (cdf) of emitter central frequency f (wide field PLE between 484.115 THz to 484.145 THz), suggesting a uniform distribution of SnV centers within this frequency spectrum. b, The cdf of the emitter linewidth smaller than Δv, suggesting 20% of emitters have linewidths (inclusive of spectral diffusion) that are within twice the transform-limited linewidth (30 MHz). In the context of optical addressability for the two spin states, color centers with a frequency variation below 200 MHz are considered suitable, accounting for 35% of the sample. c, The cdf of the SnV ZPL inhomogenous frequency in a FOV, aligning with the near-linear ZPL distribution in a narrow range. d, The cdf of the energy splitting larger than ΔE under a 0.13 T magnetic field, revealing 80% of ΔE splitting exceed 0.6 GHz.

Extended Data Fig. 7 Strain tuning mechanism and simulation in COMSOL Multiphysics.

a, The crossbar structure CMOS circuit diagram, capable of applying individual voltage control to the capacitance of each pixel region. b, The circuit in the manuscript, multi-columns are combined to facilitate global bias control. A cross-section image is shown as the sample of the circuit region on the right. c, The initial CMOS chip from vendor. d, The post-processed CMOS chip design with metalization (labeled in the yellow color, the initial CMOS metal routing is in white color. The chip post-processing metal location highlights the top electrode appearance. Wire bonding is applied to these post-processed metal areas, connecting them to an external Keithley voltage source. e, A zoom-in top-view region of the post-processed device layer. f, Device strain tensor XX component eXX distribution across the cross-section of the xz plane at y = 0.1 μm in COMSOL simulation. A bias of 10 V is applied between the CMOS backplane and the top ground electrode. g, Zoomed-in eXX strain distribution in the xz plane, with the cavity region on the x-axis ranging from –3 μm to 3 μm and y = 0 μm. heXX strain distribution in the xy plane with the cavity region at z = 57.5 nm, illustrated by the dashed line in f. The two dashed lines in h shows the xz plane position in f and g respectively. ieXX strain relation with bias voltage for the location marked with a gray triangle in f. j, The transient eXX response when the bias voltage is 10 V at the location marked with a gray triangle in f.

Extended Data Fig. 8 The spin state measurement result without post-selection.

a, Pulse control sequence. bd, Histogram plots of the spin readout results for the three APD time bins in Fig. 4b, presented without post-selection. e, Readout histogram without post-selection, featured a zoomed-in histogram in the inset. f, Correlation between the second and third APD time bins, with the correlation plot divided into four quarters, each represented by a different color: gray region (C2 < nm, C3 < nm), red region (C2 < nm, C3 > nm), blue region (C2 > nm, C3 < nm), and magenta region (C2 > nm, C3 > nm). nm is fit from b here, contrasting with nm, which is derived from the post-selected data. In the gray area, we consider the spin to be not initialized to the correct charge state, since APD bins 2 and 3 are both considered dark in the readout result. In the red area, we consider the successful spin preparation and measurement as expected. In the blue and magenta regions, the readout is considered an error for state preparation and measurement. g, The histogram of the espam statistics without post-selection. The red rectangle represents the change of espam after post-selection corresponding to the data in the manuscript Fig. 4b.

Extended Data Fig. 9 The optical measurement setup for the hardware architecture demonstration.

The setup includes the cryogenic system, laser source, 4f confocal system, SLM excitation, collection box including the duo camera image system (EMCCD and scientific CMOS camera), and collection APD detectors. The resonant laser here is modulated by an AOM and EOM, and mixed with the green repump laser via a dichroic mirror. For SLM excitation, the laser’s polarization is optimized with a half-waveplate (HWP) and quarter-waveplate (QWP) before reaching the PBS. A Faraday rotator alters the laser polarization, allowing the SLM-modulated laser signal to be reflected into the cryostat by the PBS. A beam expander (BE) enlarges the beam to cover most of the SLM pixels. The excitation laser beams enter the cryostat through a 4f system (Lenses L1 and L2) after passing through a galvo, which maps the objective back aperture and galvo plane. An HWP and QWP are positioned just before the cryostat window to adjust the setup for cross-polarization or co-polarization collection. The optical setup is designed to confocally collect photons from the quantum emitter, with the signal passing through a PBS. Situated between two lenses (L3 and L4) in the image plane, a movable D-shaped mirror reflects a portion of light in the image plane (depending on the mirror’s location) to another optical path, which is then followed by the camera, galvo, and single-mode fiber collection. A scientific CMOS camera monitors the reflected sub-FOV. By adjusting the HWP, the collection signal can be directed either to the camera path or the confocal collection path, which can enter either the free-space APD or fiber-coupled APD for collection via a programmable flippable mirror.

Extended Data Fig. 10 Approach of the all-to-all routing of photons from quantum emitters.

The D-shaped mirror divides the FOV into two sub-FOVs, each monitored with a scientific CMOS camera. The galvo positions are calibrated with potential color center candidates. Photons from each sub-FOV can be collected into single-mode fibres using corresponding galvos. The collected photons then pass through a fiber beam splitter, followed by a ZPL filter and APD for interference measurement.

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This zipped folder contains raw data for Figs. 3–5 and Extended Data Figs. 5–8.

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Li, L., Santis, L.D., Harris, I.B.W. et al. Heterogeneous integration of spin–photon interfaces with a CMOS platform. Nature 630, 70–76 (2024). https://doi.org/10.1038/s41586-024-07371-7

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