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DNA-based programmable gate arrays for general-purpose DNA computing


The past decades have witnessed the evolution of electronic and photonic integrated circuits, from application specific to programmable1,2. Although liquid-phase DNA circuitry holds the potential for massive parallelism in the encoding and execution of algorithms3,4, the development of general-purpose DNA integrated circuits (DICs) has yet to be explored. Here we demonstrate a DIC system by integration of multilayer DNA-based programmable gate arrays (DPGAs). We find that the use of generic single-stranded oligonucleotides as a uniform transmission signal can reliably integrate large-scale DICs with minimal leakage and high fidelity for general-purpose computing. Reconfiguration of a single DPGA with 24 addressable dual-rail gates can be programmed with wiring instructions to implement over 100 billion distinct circuits. Furthermore, to control the intrinsically random collision of molecules, we designed DNA origami registers to provide the directionality for asynchronous execution of cascaded DPGAs. We exemplify this by a quadratic equation-solving DIC assembled with three layers of cascade DPGAs comprising 30 logic gates with around 500 DNA strands. We further show that integration of a DPGA with an analog-to-digital converter can classify disease-related microRNAs. The ability to integrate large-scale DPGA networks without apparent signal attenuation marks a key step towards general-purpose DNA computing.

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Fig. 1: Schematic workflow of DPGA programming.
Fig. 2: Uniform dual-rail computing units with logic-gated DNA–UTS transmission.
Fig. 3: Intra- and inter-DPGA transmission mediated by wiring instructions.
Fig. 4: DPGA reconfiguration for multitask operation.
Fig. 5: Computing circuits implemented by multiple DPGAs.
Fig. 6: Nonlinear KIRC classification using integrated DPGAs.

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Data availability

The data that support the findings of this study are available in the manuscript or the Supplementary Information. Source data are provided with this paper. All other data is available on request.

Code availability

Source codes used in this study (Visual DSD, MATLAB, Python) are available from GitHub ( All other codes are available from the corresponding authors on reasonable request.


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We thank L. Qian (Caltech) and Y. Huang (Peking University) for helpful discussions. This work was supported by the National Key R&D Program of China (grant no. 2021YFF1200300), the National Natural Science Foundation of China (grant nos. T2188102, 21991134, 21904060, 22025404 and 22104088), the Science Foundation of Shanghai Municipal Science and Technology Commission (grant nos. 20dz1101000 and 21TQ1400222) and the New Cornerstone Investigator Program. Molecular dynamics simulations were run on the π2.0 cluster supported by the Center for High Performance Computing at Shanghai Jiao Tong University.

Author information

Authors and Affiliations



C.F. and F.W. conceived the research. F.W. designed the circuits and wrote the sequence-generating and -compiling programmes. H.L. performed the majority of the experiments. N.X. performed AFM experiments. C.S. and Q.Z. performed magnetic field-related experiments. M.L. and F.W. performed simulations. L.Z. trained the nonlinear classification model. F.W., C.F. and H.L. analysed data and wrote the manuscript. M.D., J.L. and H.C. participated in data analysis and discussions. C.F., H.C., J.L., N.X., M.D. and X.Z. reviewed and edited the manuscript.

Corresponding authors

Correspondence to Fei Wang or Chunhai Fan.

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Extended data figures and tables

Extended Data Fig. 1 Outline of the design strategy for general-purpose DICs.

a, Architecture for electronic chips integration. b, Hierarchical illustration of scalable DPGA integration (shown by the logical arrangement). We referred architectural properties of programmable electronic integrated circuits to design general-purpose DICs. In electronic integrated circuits, general-purpose chips can be physically integrated, with the information exchange between chips and storage realized via electrons. Analogous to electronic signal, DNA-UTS is used to transmit information. Inter-gate and inter-DPGA information transmission are all enabled by DNA-UTS. With uniform transmitted signals, integrability is permitted both at the gate and the DPGA levels. Asynchronous execution of cascaded DPGAs interdicts molecular diffusion between DPGAs, allowing DPGA integration. Hence, the scalability is enabled with the use of DNA-UTS and DNA origami register. In addition, arbitrary gate connection is allowed in a DPGA, providing rich programming space. In all, the programmability and the scalability support general-purpose computing with DICs.

Extended Data Fig. 2 Representative DNA circuits experimentally implemented via multi-level programming of DPGAs.

The DIC is composed of three levels: DNA gates; DPGAs and DPGA networks.

Extended Data Fig. 3 Demonstrated advantages of dual-rail gates.

a, A single-rail gate receives one molecule as an input and generates one molecule as output. The concentration of output increases rapidly when the output is 1 while slowly when the output is 0. b, A dual-rail gate receives a molecule representing 1 or another molecule representing 1 as an input, and generates one molecule as output = 0 or another molecule as output = 1. The output signal is represented by the difference of two output signals. When output = 1, the output signal increases; when output = 0, the output signal decreases. c, Implemention of a dual-rail XOR gate with AND-OR gates requires six gates. d, Left, heatmap showing the result values with all possible combinations of high and low signals, when a result is supposed to be 0. Triangular region above the upper red line represents the obtained dual-rail results smaller than 0.4. Right, heatmap of error flag with all possible combinations of high and low signals. Regions inside the green box have error flag values lower than 0.4. e, Five possible computing states for a result supposed to be 0. f, Left, heatmap showing the result values with all possible combinations of high and low signals, when a result is supposed to be 1. Triangular region below the lower red line represents the obtained dual-rail result larger than 0.6. Right, heatmap of error flag with all possible combinations of high and low signals. Regions inside green boxed have error flag values lower than 0.4. g, Five possible computing states for a result supposed to be 1.

Extended Data Fig. 4 Internal structures and operating mechanisms of the four dual-rail gates.

a, Schematics showing internal structures of the dual-rail gates. AND gate has two series switches to respond to in1H and in2H respectively, generating outH in the presence of both in1H and in2H. Another switch responds to both L inputs, generating ouL in the presence of either in1L or in2L. OR gate has an opposite internal structure of AND gate. NOT gate has two switches, one for L input and one for H input. XOR contains four input-controlled switches. b–e, Signal transmission paths with all possible input combinations for AND (b), OR (c), NOT (d) and XOR (e) gates. High signals are shown in red and low signals in green. Single-stranded inputs bind to logic gates and release the corresponding output strands through SDRs. For AND gate, both in1L (representing in1 = 0) and in2L hybridize with s1 to displace s2 (=outL). in2H hybridizes with S3 to displace S5, exposing toehold γ for in1H to replace S4 (=outH).

Extended Data Fig. 5 The complete simulated time trajectories (a) for Fig. 2e and distance distributions during the simulation time (b).

With 1-nt gap, the toehold domain bound reversibly to S3 (middles panel of Distance 1 trajectory, inset), which did not lead to further branch migration (high fluctuation for Distance 2 and 3). Therefore, the presence of only in1H cannot generate a fault result, permitting neglectable leakage similar to that of 0-nt gap. However, 2-nt gap allowed stable binding of in1H (left panel of Distance 1 trajectory, indicated by H-bond arrow), and the output strand was replaced via branch migration (left panels of Distance 2 and 3 trajectories, indicated by H-bond arrows). Insets in (b): Distributions of Distance 1 ranging from 0.5 nm to 2.5 nm.

Extended Data Fig. 6 Experimental optimization and performance evaluation of WIR2 and WIR3.

a, Molecular reactions for wiring (for WIR2) or reading out (for WIR3) an output signal from a gate. Low (green) and high (red) signals are transmitted independently. The dashed lines indicate the upstream binding region. b, To introduce the threshold-over-amplifier binding priority, the duplex region was shortened by 2 bp, which minimized non-specific input-threshold binding and the leakage. c, Without Threshold, output from a gate could be amplified to close to 1. However, weak signal leakage could also be amplified, leading to false result. Thus, the threshold is essential to suppress leakage before amplification. d, We used a Threshold molecule (Th) that could interact with output quickly. With 0.4× leakage signal, we found Th with a concentration higher than 0.4× can effectively suppress leakage. With 1× output signal, we found signal transmission speed decreased with Th concentration. To balance leakage suppression and computing speed, we used 0.4× to 0.6× Threshold for experiments. e, Signal wiring for High signal (left) and Low signal (right) using 0.4× threshold.

Source Data

Extended Data Fig. 7 A representative compiling process of the DNA Compiler.

Statements containing different type of operations and different priorities can be compiled into wiring instructions to configure DPGA.

Extended Data Fig. 8 The signal relay function of WIR4s.

a, Possible transient binding reactions between unmatched molecules that may affect the circuit performance. b, Numerical simulation of the computing process from upstream inputs to downstream inputs considering the transient binding. With the increase of the circuit size, the exposed toeholds have a higher chance of being occupied by unmatched strands via transient binding, leading to reduced computing speed. c, Experimental computing kinetics of an OR gate when 0, 500, 1000 and 1500 nM unmatched threshold molecules were added, respectively. d, Dual-rail results of the OR gate followed by a WIR3 at different unmatched threshold levels. e, The 11-layer cascade circuit in Fig. 3g when implemented with a single DPGA. f, Simulated computing kinetics of 1- to 11-layer subcircuits implemented with a single DPGA without WIR4. g, Simulated dual-rail results of the cascade circuit showing decayed performance with the increase of the circuit depth, which is generally consistent with the experimental results. h, Circuit diagram of a cascade circuit containing 11 layers of dual-rail gates, which was divided and implemented by three configured DPGAs. i, Simulated computing kinetics of the subcircuits in the cascaded DPGAs connected by WIR4s.

Extended Data Fig. 9 Signal decay during the cascade of DPGAs.

a–b, Illustration of the circuit depth. The largest circuit depth (a) and the corresponding SDR pathway that contains 30 steps of reactions (b), beyond what can be achieved with a single reaction. c, Schematic illustrations showing tested systems with direct ideal input and that transmitted by WIR4s. d, Paired comparison showing the increase of the half-competition time (t1/2). d–g, Output, leakage and error showing insignificant difference between DPGAs using direct input and transmitted input.

Source Data

Extended Data Fig .10 Computing kinetics of 20 experimentally tested samples in addition to that in Fig.  6g in test set.

The values in bracket show the normalized concentration of mir-200c, mir-204 and mir-887, respectively.

Source Data

Supplementary information

Supplementary Information

Methods, texts, Figs. 1–62, Tables 1–7 and references that extend and support the data and discussion presented in the main text.

Supplementary Data 1

DNA sequences used in each figure.

Supplementary Data 2

DNA sequences for dual-rails gates and wiring instructions.

Supplementary Data 3

Information and experimental results of 103 circuits for robustness evaluation.

Peer Review File

Source data

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Lv, H., Xie, N., Li, M. et al. DNA-based programmable gate arrays for general-purpose DNA computing. Nature 622, 292–300 (2023).

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